April 2006 www.rtcmagazine.com An RTC Group Publication CompactPCICompactPCI BRINGS SWITCHED FABRICS INTO THE BACKPLANE ZigBee Wireless Networking for Sensors High-Speed and Hybrid Backplanes Real-Time Java Also in this issue The magazine of record for the embedded computing industry
Typical Linux kit includes: • Target CPU card • Preloaded OS image on 256 MB industrial CompactFlash • 256 MB SO–DIMM module • Interface cables • Hard copy of manual • Mouse • CPU OS bootable CD • Optimized OS version • Full driver support for on–board hardware • X–Windows support • Example applications and source code • Extra documentation Our kits are the shortest path to a successful OS on an Octagon embedded computer. • Pick your Octagon SBC • Pick the OS you prefer: Linux, Windows, QNX Octagon delivers a high performance, total solution. Features XE–900 XE–800 XE–700 CPU Via Eden AMD Geode GXI STPC Clock speed 400 MHz; 733 MHz; 1.0 GHz 300 MHz 133 MHz BIOS General Software Phoenix Phoneix DRAM support to 256 MB to 256 MB 32/64 MB Compact/Flash Type I or II Type I or II Type I or II COM 1 RS–232 RS–232/422/485 RS–232 COM 2 RS–232 RS–232/422/485 RS–232/422/485 COM 3 RS–232 NA RS–422/485 COM 4 RS–232 NA RS–232 COM 5 RS–232/422/485 NA NA COM 6 RS–422/485/TTL NA NA LPT1 0 0 1 EIDE 2 2 1 USB 2 6 2 CRT 1600 x 1200 1280 x 1024 1280 x 1024 Flat panel LVDS yes yes Digital I/O 24–bit prog. 48–bit prog. 24–bit prog. Ethernet 10/100 Base–T Dual 10/100 Base–T 10/100 Base–T Expansion PC/104 & Plus PC/104 & Plus PC/104 Power 3.6A operating 1.6A max. 1.6A max Temp. range –40° to 70/85° C –40° to 80° C –40° to 80/85° C Shock/vibration 40/5g 40/5g 40/5g EPIC™ XE–900 1.0 GHz CPU
XBLOKs offer the best compromise in cost and function for both PC/104 and PC/104-Plus. Only 44% the size of a standard PC/104 card, you can add two functions to your system but increase the stack height by only one level. –40° to 85° C. Heat diagram shows enhanced cooling. Designed for the XE-900, our conduction cooling system eliminates a fan even at 1.0 GHz. X–SRAM–2 MB • 2 MB high speed, SRAM • Read and write at full bus speed • Pointers to memory saved if CPU resets or loses power X–DIO–48 bit programmable digital I/O • 48 digital I/O, 5V compatible • Source and sink 16 mA per output • Direct connection to opto-module racks X–COM–2 dual UART • Up to 230.4 kBaud data rate • Supports RS–232/422/485 • RS–485 fault protected to ±60V X–LAN–1 Ethernet LAN • 10/100 Base–T, Intel 82551ER • Fully plug–n–play • High performance, PCI bus interface X–USB–4 quad USB 2.0 • Speeds up to 480 mbps • Mix and match USB 1.1 and 2.0 • Current–limited ports can supply 500 mA to external devices XBLOKs offer the best compromise For a full listing of Octagon Systems products, visit us at www.octagonsystems.com Designed for the our conduction cooling system eliminates a fan even at 1.0 GHz.
SBS knows AdvancedMC™. Get from ATM to IP on one board. SBS knows. Find the AdvancedMC board you’re looking for at www.sbs.com/amc or call 800.SBS.EMBEDDED FITTING A GATEWAY that converts ATM to IP on an AdvancedMC™ wasn’t exactly easy, but we did it. And while we were at it, we included the high availability features we knew you’d be looking for, like Automatic Protection Switching, Hot Swap, IPMI v1.5 for integrated management support and Carrier Grade Linux® driver support. The Telum 1204-O3 is essentially a gateway in an AdvancedMC format specifically designed to facilitate the migration from legacy networks to IP-based networks. This board is ideal for any application where local Ethernet traffic needs to seamlessly access a wide area network using OC-3. The Telum 1204-O3 module’s versatile inter- working capabilities allow it to independently interconnect between any supplied protocols, which can be selected on a per-por t basis. For increased adaptability, a full set of IP ser vices can be offered over any Layer 2 protocol including ATM AAL5, PPP and Ethernet. T his pro duc t is f lex ible and s of t ware configurable, allowing you to support a wide range of existing protocols as well as emerging standards. For a full description of features, please visit www.sbs.com/amc. Prepare to be amazed. That’s an ATM to IP gateway?
Features www.rtcmagazine.com April 2006 Departments 9 Editorial: Brave New Multicore World 10 Industry Insider 8 Products&Technology 6 A Delegation RTOS Can Slice Low-Value (Boring) Work from Real-Time System Projects Victor Yodaiken, FSMLabs 69 You Don’t Have to StopHigh-Availability Systemsfor Updates Pat Rogers and Cyrille Comar, AdaCore Industry Watch 3 Achieving RAMS Objectives in Hard Real-Time Java Software Kelvin Nilsen, Aonix Real-Time JavaSoftware & Development Tools 47 RTC Interviews Pat Busby, CEO of Diversified Technology Executive Interview 32 Advanced Switching on CompactPCI Express Steve Cooper, One Stop Systems 37 CompactPCI Express Links the Past and Future Paul Gaudreau, Inova Computers 43 System Scalability with Switched Fabrics in CompactPCI Tom Cox, RapidIO Trade Association CompactPCI and Switched FabricsIndustry Insight 20 VXS Processor Mesh Architecture: Powerful, Flexible, Compatible Michael Munroe, Elma Bustronic 26 Functionality and Design of AdvancedTCA Backplanes Andreas Lenkisch, Schroff High-Speed and Hybrid BackplanesSolutions Engineering 14 Using ZigBee Wireless Networking to Develop Commercial Products Jon Adams, Freescale Semiconductor I/O and Sensor TechnologyTechnology in Context ZigBee/802.15.4 Mesh network and device types. • Pg. 14 Tiny Industrial Device Server Simplifies Factory Connections. • Pg. 8 New connectors and pin outs enhance CompactPCI boards to incorporate PCIe functionality and performance. • Pg. 32 ZigBee Coordinator ZigBee Router ZigBee End Device
6 April 2006 April 2006 Publisher PRESIDENT John Reardon, johnr@r tcgroup.com VICE PRESIDENT, European Operations Zoltan Hunor, zoltanh@r tcgroup.com EDITORIAL DIRECTOR/ASSOCIATE PUBLISHER Warren Andrews, warrena@r tcgroup.com Editorial EDITOR-IN - CHIEF Tom Williams, tomw@r tcgroup.com SENIOR EDITOR Ann Thr y f t, annt@r tcgroup.com MANAGING EDITOR Marina Tringali, marinat@r tcgroup.com STAFF EDITOR Craig Choisser, craigc@r tcgroup.com COPY EDITOR Rochelle Cohn Art/Production CREATIVE DIRECTOR Jenna Hazlett, jennah@r tcgroup.com GRAPHIC DESIGNER Melissa Gaeta, melissag@r tcgroup.com PRODUCTION DESIGNER Kirsten Wyatt, kirstenw@r tcgroup.com DIRECTOR OF WEB DEVELOPMENT Jan Garcia, jang@r tcgroup.com WEB DEVELOPER Marke Hallowell, markeh@r tcgroup.com Advertising/Web Advertising CALIFORNIA COASTAL ADVERTISING MANAGER Diana Duke, dianad@r tcgroup.com (949) 226 -2011 WESTERN REGIONAL ADVERTISING MANAGER Lea Ramirez, lear@r tcgroup.com (949) 226 -2026 EASTERN REGIONAL ADVERTISING MANAGER Nancy Vanderslice, nancy v@r tcgroup.com (978) 443 -2402 EMEA SALES MANAGER Anna Brown, annab@r tcgroup.com (949) 226 -2025 ASIAN ADVERTISING MANAGER John Koon, johnk@r tcgroup.com (858) 755 - 4999 Billing Maggie McAuley, maggiem@r tcgroup.com (949) 226 -2024 To Contact RTC magazine: HOME OFFICE The RTC Group, 905 Calle Amanecer, Suite 250, San Clemente, CA 92673 Phone: (949) 226-2000 Fax: (949) 226-2050, www.rtcgroup.com EASTERN SALES OFFICE The RTC Group, 96 Dudley Road, Sudbury, MA 01776 Phone: (978) 443-2402 Fax: (978) 443-4844 Editorial Office Warren Andrews, Editorial Director/Associate Publisher 39 Southport Cove, Bonita, FL 34134 Phone: (239) 992-4537 Fax: (239) 992-2396 Tom Williams, Editor-in-Chief 245-M Mt. Hermon Rd., PMB#F, Scotts Valley, CA 95066 Phone: (831) 335-1509 Fax: (408) 904-7214 Ann Thryft, Senior Editor 15520 Big Basin Way, Boulder Creek, CA 95006 Phone: (831) 338-8228 Published by The RTC Group Copyright 2006, The RTC Group. Printed in the United States. All rights reserved. All related graphics are trademarks of The RTC Group. All other brand and product names are the property of their holders.
© 2006 National Instruments Corporation. CompactRIO, LabVIEW, National Instruments, NI, and ni.com are trademarks of National Instruments. Other product and company names listed are trademarks or trade names of their respective companies. 2006-6658-821-101-D Design to Deployment with One Graphical Environment Design with LabVIEW Interactive algorithm design tools Native simulation capabilities Built-in analysis and I/O Prototype with LabVIEW Reconfigurable FPGA I/O COTS prototyping platform Deploy with LabVIEW 32-bit processor deployment Same environment from algorithm design to implementation Graphical Development Platform for Design, Control, and Test • Intuitive embedded programming representation • Rapid application development • Built-in I/O connectivity and ready-to-run analysis Improve your productivity with LabVIEW graphical system design. View technical tutorials online at ni.com/labview/embedded. (800) 890 6229
Embedded Performance. ©2006 GE Fanuc Automation. All rights reserved. GE Fanuc Automation CPCI-7808 Intel Pentium M CompactPCI Single Board Computer • PICMG 2.16/2.9 compliant • Processor speeds up to 1.8 GHz • Up to 2 GB DDR SDRAM • Dual PMC sites - 64-bit/66 MHz site - 32-bit/33 MHz site • Dual 10/100/1000 Ethernet interface • Dual 16550-compatible serial ports • Three USB 2.0 ports • Serial ATA interface • Up to 1 GB CompactFlash • OS support for Windows XP, Windows 2000, QNX, Linux, and VxWorks ATCA-7820 AdvancedTCA Dual Core Intel Xeon Processor LV 2.0 GHz Processor Node Board • Combines two dual core processors, providing four high performance cores • PICMG 3.0/3.1 compliant • Processor speeds up to 2.0 GHz • Up to 8 GB DDR-2 SDRAM with ECC • AMC.1 compliant site (PCI-Express x 8) • Single PCI-X PMC site at 64-bit/66 MHz • Single 10/100 Ethernet interface • Dual serial ports • Four USB 2.0 ports • Serial ATA interface • Optional 2.5-inch IDE hard disk drive • OS support for Windows XP, Windows 2000, and Carrier Grade Linux PMC-0247 Serial ATA Hard Disk Drive Module • 40 Gbyte or 80 Gbyte options available • Support for SATA I (150 Mbps) and SATA II (300 Mbps) interfaces • Support for programmable External Flash for BIOS expansion • Supports 32/64-bit, 133 MHz maximum PCI-X interface • Fast read/write performance • VITA 39 compliant • OS support for Windows XP, Windows 2000, Red Hat Linux‚ and Enterprise 4.0 Looking for an embedded computing solution that gives you a tremendous advantage over your competition? Look no further than GE Fanuc Embedded Systems. Featuring a comprehensive offering that includes Intel-based SBCs and complete I/O systems, industry-leading communications technology, rugged flat panel monitors and computers and more, GE Fanuc Embedded Systems can support your full range of embedded computing needs to solve your greatest challenges. From standard product requests to a solution that is quickly and fully customized to your specific application, GE Fanuc Embedded Systems has the breadth, depth and support capabilities to provide a serious boost to your performance. Learn more at www.gefanuc.com/embedded CP920 CompactPCI Managed Gigabit Ethernet Switch • PICMG® 2.16 compliant • Layer 2/3/4 switching • Twenty-four 10/100/1000 Ethernet ports • PICMG® 2.9 Rev 1.5 IPMI compliant • PICMG® 2.1 Rev 2.0 hot swap compliant • 802.1p, 802.1Q VLAN, deep packet filter- ing, link aggregation, Rapid Spanning Tree (802.1w, 802.1d), broadcast storm control, port mirroring • Conduction cooled model available – Twelve 10/100/1000 Ethernet ports
April 2006 9 Editorial April 2006 W ill multicore architectures move us forward? There seems to be quite a bit of movement in the industry. Chips are coming out of fabs, they are going onto boards, they are generating buzz and software developers are gearing up to ad- dress their needs with updated tool suites. Not only that, the vari- ety of multicore architectures appears to be shaping up to address different application needs. The obvious advantage is that with the ability to cram more transistors onto a die, we can implement parallelism. That lets code execute faster without the brute-force step of simply flog- ging the silicon harder. The result is faster execution with less power consumption and less heat dissipation. This is, of course, the Holy Grail for embedded. These appear to be falling into several categories. One might be called “general purpose” with several copies (most commonly two or four) of a CPU architecture. We are already seeing these with architectures from Intel, AMD and ARM. Even these can have variants. For example, individual CPUs might have a shared cache memory, or each may have their own cache. This has, of course, implications as to how the software is partitioned and ex- ecuted. Several embedded operating system vendors are already on board with support for these processors. For the embedded application developer, there are fewer has- sles than I, at least, had initially assumed. Since embedded and real-time code is inherently multi-threaded, most issues of appli- cation partitioning are minimal for the developer wishing to port code to these new architectures. Optimizing new code may take more thought and effort, but with dual- and quad-core processors coming onto the market and already being integrated into OEM board-level products with initial RTOS support, we should see some real application improvements in the fairly near future. The eight-CPU Cell processor from IBM has recently made its transition from the game box to high-end medical instrumen- tation and military surveillance. A block diagram of the Cell is like looking at the diagram of a multi-board bus-based system, except that it’s all on a single die. It has reduced that task of pro- cessing raw sensor data into high-resolution graphics to a real- time operation. This has significant implications. Now an unmanned aerial vehicle (UAV) can integrate its sensor data into real-time graphic frames and transmit the ren- dered frames to the ground operator. This reduces the amount of data transmission as well as eliminating the time required to process it into a display on the ground. There are, of course, more exotic versions of multicore pro- cessors. One design is a dataflow architecture consisting of a matrix of 16 x 16 8-bit processing elements that the company, Rapport, says it will eventually expand to a 4096-element pro- cessor. Of course, such an architecture addresses a more narrow set of functions such as security decryption, high-speed graph- ics and signal processing operations. It also requires compilers and development tools more specifically tailored to its architec- ture. Then there are the FPGA-based multicore processors. The type of soft processor cores offered by companies like Altera and Xilinx are getting third-party IP that can harness multiple copies into a multicore, load balancing design. Multicore is definitely with us and here to stay, and as with all relatively new developments, it’s safe to say, “you ain’t seen nothin’ yet.” Look for performance increases coming soon and even better developments down the road. Brave New Multicore World by Tom Williams, Editor-in-Chief
10 April 2006 INDUSTRy INSIDER April 2006 Mesh Networking Proposal Selected for IEEE 802 Wireless LANs The IEEE 802.11 Working Group has passed a major milestone in the development of IEEE 802.11s, “Wireless LAN Medium Access Control (MAC) and Physical Layer (PHY) Speci- fications: Extended Service Set Mesh Networking,” by voting to confirm a single proposal as the initial basis for the IEEE 802.11s standard. Many additional steps, which will include technical changes, are necessary before this standard becomes final; but this vote sets the baseline from which the group will work. Once completed, IEEE 802.11s will provide an interoperable and secure wireless distribu- tion system between IEEE 802.11 mesh points. This can reduce backhaul and installation costs. It also will extend mobility to access points in IEEE wireless local area networks (WLANs), enabling a new class of IEEE 802.11 applications that require untethered infra- structure. The working group winnowed the 15 proposals presented in July 2005 for this amend- ment down to two in January 2006. The two final concepts were then merged to create a joint proposal, which the group confirmed as a baseline for this amendment. The evaluation pro- cess considered five relevant use cases, i.e., those concerning the residential, office, public safety, military and campus/community/public access sectors. Siemens Joins Highest Level of ZigBee Alliance The ZigBee Alliance, a non-profit industry association promoting the growth of a global, open standard for wireless control of devices used to automate homes, commercial buildings and industrial environments, has announced that Siemens has been admitted at the highest level of membership—“Promoter” level. Siemens joins BM Group, Ember Corporation, Freescale Semiconductor, Honeywell, Mitsubishi Electric, Motorola, Philips, Samsung and Texas Instruments on the ZigBee Alliance Board of Directors. ZigBee is a standards-based technology designed to address the needs of low-cost, low-power, wireless sensor networks for remote monitoring, home control and building automation network applications in the industrial and consumer markets. Siemens’ support and leadership commitment to the ZigBee Alliance comes on the heels of the recent moves by several industry giants: Texas Instruments completed its acquisition of Chipcon in January, and a joint effort by STMicroelectronics and Ember to work together on ZigBee solutions was also completed in January. Siemens will implement ZigBee technology in sensors used in discrete manufacturing and process automation in conjunction with existing communication standards like Profibus and Profinet. The Alliance is now more than 200 members strong and has a presence in 26 countries spanning six continents. OEMs and end-product manufacturers represent 37 percent of the global membership. Companies who want to have input on developing ZigBee applications and create ZigBee products can visit www. zigbee.org/join/. GE Fanuc Completes Acquisition of Condor Engineering GE Fanuc Embedded Systems has announced that it has completed the acquisition of the technology assets of Condor Engineering including test and simulation products, embedded boards and core technology designed to meet the data communications needs of commercial and military aircraft manufacturers and suppliers. The Condor product set includes powerful hardware interface solutions for application engineers, extensive high- level API libraries for software developers, GUI monitor and control programs for integrators and test engineers, and core logic for embedded designers. This robust technology supports F-16, F-18, F-22, C-17, C-130, Airbus and Boeing aircraft. Test and Simulation products include COTS avionics communications solutions including CompactPCI, PCI, PMC and VME platforms. The former Condor Engineering team has been designated as the “center of excellence” for GE Fanuc avionics interface products, continuing to provide a high level of technology expertise and customer care in producing quality products to meet the needs of this industry. TI and Altera Partner for Low-Cost PCI Express Texas Instruments and Altera have announced the availability of a low-cost, PCI- SIG-compliant solution that reduces the cost and accelerates the development of PCI Express- based systems. Suited for video cards, data acquisition, test and network equipment, and various embedded applications, the offering includes TI’s XIO1100 PCI Express x1 physical layer (PHy) chip, Altera’s low-cost Cyclone II FPGAs and PCI Express x1 MegaCore intellectual property (IP) function. TI and Altera began partnering in early 2005 to develop this PCI Express solution. As a result, the solution has been thoroughly tested at the protocol and board levels, ensuring total interoperability between the two devices. It was approved by PCI SIG, the industry forum for developing PCI Express specifications and performing interoperability. This low-cost solution builds
Call us toll-free at (866) 4-ADLINK or email info@adlinktech.com An Entire Family of High-Speed, Low-Power Universal Intel® Pentium® M Processor Boards The cPCI-6840 family combines Intel's latest high performance low power processor the Pentium® M with the 855GME MCH and two different I/O controller hubs. The Pentium® M has a highly efficient instruction execution unit and coupled with a large L2 cache, it can outperform other processors at the same clock speed. The 855GME has an integrated 250MHz 32-bit 3D/2D graphics engine capable of supporting simulations CRT and flat panel displays. The ICH packs a plethora of peripherals include Serial ATA 150, PATA, USB 2.0, watchdog timer and serial port. For more info, go to: www.adlinktech.com/products www.adlinktech.com 3U CompactPCI Board based on Intel® Pentium® M Processor with ntel® 855GME Chipset The cPCI-3840 is a 3U CompactPCI Pentium® M processor board. Combined with embedded chipsets 855GME and 6300ESB, the cPCI-3840 offers up to 2GB DDR 333 memory with XVGA and flat panel graphics, dual Gigabit Ethernet ports, and several I/O features. It delivers higher computing power but at low-power consumption. The cPCI-3840 is specially designed for industrial automation and control system applications. For more info, go to: www.adlinktech.com/products Full-size ePCI-X SBC featuring Intel® Pentium® 4 Processor with HT Technology The NuPRO-850 features high computing capability and supports 800/533MHz FSB hyper-threading Pentium® 4. This product incorporates a PCI-X bus for 64-bit/66MHz performance. It has high bandwidth to support AGP8X performance VGA display and Serial ATA for high speed storage. The NuPRO-850 also supports USB 2.0 and generic features such as COM, KB, mouse and hardware monitoring. For more info, go to: www.adlinktech.com/products ETXexpress Computer-on-Module with Intel® Pentium® M Processor As the first member of ADLINK's ETXexpress family, the ETXexpress-IA533 uses a low power Intel® Pentium® M processor 760 at 2.0GHz and the Mobile Intel® 915GM Express Chipset. Both the chipset and processor are part of the embedded Intel® Architecture that ensures a long production life for applications that need extended availability. The ETXexpress-IA533 supports dual channel DDR2 533MHz memory and comes with a single on-board Gigabit Ethernet port. In addition to the onboard integrated graphics, a Graphic PCI Express x16 slot is also available. The board connects up to four additional PCI Express x1 devices. The module has legacy support for 32-bit PCI and ISA through LPC. For more info, go to: www.adlinktech.com/products �Standard 6U CompactPCI and PICMG 2.5 H.110 CT Bus �PICMG 2.1 Hot Swap compliant 64-bit 8-slot CompactPCI backplane with P3 & P5 rear I/O �2+1 Hot Swappable 500W+250W Redundant Power Supply with Universal AC input �Guarded Power Switch and Reset Button �Dual AC-inlet for Dual AC-input (DC input optional) �LED Indication for Power Status, Fan Status, Temperature Alarm �Embedded a Chassis Management Tool to Monitor (fan, temperature & voltage) via RS-232 port
12 April 2006 INDUSTRy INSIDER Event Calendar 04/25/06 Real-Time & Embedded Computing Conference Greenbelt, MD www.rtecc.com/greenbelt 04/27/06 Real-Time & Embedded Computing Conference Boston, MA www.rtecc.com/boston 05/09-10/06 FSA Suppliers Expo – Europe & IEE/FSA Munich, Germany www.fsa.org 05/09/06 Real-Time & Embedded Computing Conference Helsinki, Finland www.rtecc.com/helsinki 05/09-10/06 AFCEA TechNet Hampton, VA www.afcea.com 05/16/06 Real-Time & Embedded Computing Conference Minneapolis, MN www.rtecc.com/minneapolis 05/16-17/06 Military Embedded Elec. & Computing Conference Long Beach, CA www.meecc.com 05/18/06 Real-Time & Embedded Computing Conference Chicago, IL www.rtecc.com/chicago 06/06/06 Real-Time & Embedded Computing Conference Dallas, TX www.rtecc.com/dallas 06/08/06 Real-Time & Embedded Computing Conference Houston, TX www.rtecc.com/houston If your company produces any type of industry event, you can get your event listed by contacting sallyb@rtcgroup.com. This is a FREE industry-wide listing. cores and development boards for endpoint, bridge, switch and root complex functionality. CAN in Automation Group Active on Multiple Standards Efforts The CAN in Automation (CiA) organization has released the CANopen multi-level networking specification (CiA 400) and the CANopen application profile for road construction machine sensor systems (CiA 415). The documents are available for CiA members. The CiA-400 specification supports the design of CANopen- based systems that use multi-level networks. It is possible to describe systems made by up to 127 CANopen networks. Each network may in turn comprise up to 127 CANopen devices. The CiA-400 gateway is able to support up to 32 CANopen interfaces. It is possible to forward Service Data Objects (SDO) as well as Emergency messages. The NMT requests and the Heartbeat information are forwarded through the entire system by remote SDO. The CiA- 415 application profile for road construction machines describes the objects for sensors and sensor controllers. This includes sensors for different temperature and position measurements. This second version of the profile has been entirely reviewed and is not compatible with the previous version. CiAstartednewstandardization activities. The CANopen Special Interest Group (SIG) crane/spreader is going to define an interface specification based on CANopen to interconnect crane control systems to spreaders. CiA is also calling for RFID experts who wish to develop a CANopen device profile for RFID reader devices. Several CANopen- based control systems require RFID information, for example in laboratory automation, storage systems, production lines, etc. The first RFID reader with CANopen connectivity is already on the market. Avnet and Kingston Announce Global Agreement Avnet Computing Components and Kingston Technology have announced a global agreement to market and distribute Kingston’s memory products across Europe, Asia Pacific and the Americas. As part of the agreement, Avnet will market and distribute Kingston’s ValueRAM and Flash memory products, concentrating on specific customer segments including value-added resellers (VARs), system builders and PC assemblers. Kingston’s high- density modules complement AMD’s Opteron technology. Free technical support also ensures Avnet’s white-box and system builders have access to 24x7 technical resources. “This is an exciting partnership for Kingston, as Avnet is uniquely positioned at the heart of the technology industry, serving the needs of the world’s leading high-tech companies,” said Hanni Eid, business development manager, Kingston. “Kingston delivers strong technical expertise and unrivaled logistical operations support. These capabilities enable both Avnet and Kingston to take advantage of new opportunities within the growing system builder market,” added Eid. George Condon, senior vice president of Avnet Computing Components, Americas, added: “Together Avnet and Kingston are offering customers memory technology that provides superior value. By combining the technical and logistical expertise within each company, we will be able to offer flexible, high- quality solutions that will be of real benefit to our customers. We know that by responding to our customers’ needs quickly, we can help them take advantage of new market opportunities and increase revenues, so it’s good news for everyone.” Thales Partners with Green Hills Software for Low-Power 1 GHz PowerPC Products Thales and Green Hills Software have announced that the two companies have entered into a partner agreement to integrate Green Hills Software’s Integrity RTOS and Multi development tools with Thales’ single board computers (SBCs). The royalty- free, total-reliability Integrity operating system and board support package from Green Hills Software is available immediately on Thales Computers’ products, starting with the Power Engine 7 family, which includes the low- power 1 GHz PowerPC 750GX (17 watts ty
Share your vision with us. We’ll customize our products to your requirements or partner with you to develop custom products all the way through deployment. Either way, you’ll get leading-edge board level w w w. v a d a t e c h . c o m 7 0 2 . 8 9 6 . 3 3 3 7 SHARE YOUR VISION. WE’LL SHARE OUR INNOVATION. solutions for the most demanding embedded applications. Tell us what you need at info@vadatech.com. • Comprehensive Hardware/Software solution for Intelligent Peripheral Management Interface (IPMI) version 2.0 • Symmetric Multi-Processing CPU for AMC/VME Modules • A complete line of ATCA and AMC carriers • High dynamic range A/D Converters
TechnologyInContext I/O and Sensor Technology 14 April 2006 Using ZigBee Wireless Networking to Develop Commercial Products ZigBee devices bring simple, effective wireless connectivity to low-rate sensors and control devices at an effective cost. The ZigBee Alliance has built up an interoperability, compliance and certification program to validate products’ performance in a ZigBee environment. by Jon Adams Freescale Semiconductor Z igBee wireless mesh technology has been developed to address sensor and control applications with its promise of robust and reliable, self-configuring and self-healing networks that provide a simple, cost-effective and battery-efficient approach to adding wireless to any appli- cation, mobile, fixed or portable. A typical IEEE 802.15.4-based, ZigBee-compliant device is shown in Figure 1. The ZigBee Alliance released their specification to the public in June 2005, and since then the playing field has be- come much simpler for product designers who want to add wireless to their sensor or control application. An open and grow- ing industry group of nearly 200 compa- nies from product/system OEMs to ap- plications developers to semiconductor companies, the Alliance has worked hard to provide a technology that takes best ad- vantage of the robust IEEE STD 802.15.4 short-range wireless protocol, adding flexible mesh networking, strong security tools, well-defined application profiles, and a complete interoperability, compli- ance and certification program to ensure that end products destined for residential, commercial and industrial spaces work well and network information smoothly. Zigbee Relies on the IEEE 802.15.4 Standard The IEEE standard brings with it the ability to uniquely identify every radio in a network as well as the method and format of communications between these radios, but does not specify beyond a peer-to-peer communications link, a network topology, routing schemes or network growth and repair mechanisms. The IEEE 802.15.4 standard, re- leased in May 2003, was selected by the ZigBee Alliance as the “wheels and chas- sis,” upon which ZigBee networking and applications are to be constructed. This is not without its challenges, as the Alliance does not control the IEEE specification. However, many of the same people who sit in the IEEE 802.15 Working Group are deeply involved in the ZigBee standard. Get Connected with companies mentioned in this article. www.rtcmagazine.com/getconnected Get Connected with companies mentioned in this article. www.rtcmagazine.com/getconnected End of Article exploration er your goal eak directly l page, the resource. hnology, and products panies providing solutions now ration into products, technologies and companies. Whether your goal is to research the latest lication Engineer, or jump to a company's technical page, the goal of Get Connected is to put you ice you require for whatever type of technology, ies and products you are searching for. Figure 1 A typical IEEE 802.15.4/ZigBee Device (including antenna, RF data modem, applications processor, all necessary passives and 16 MHz crystal, about 15 x 40 mm).
April 2006 1 TechnologyInContext This relationship has meant that both the IEEE and the ZigBee specifications track one another fairly well. Figure 2 shows the relative organization of the IEEE radio with respect to the ZigBee functionality. The IEEE standard specifies the RF link parameters, including modulation type, coding, spreading, symbol/bit rate and channelization. Currently, the stan- dard identifies 27 channels spread across three different frequency bands (Table 1). The 802.15.4 PHy physical layer contains specific primitives that man- age the radio channel, and control packet data flow. This is a packet radio specifica- tion, and the PHY defines four different frames that have unique functions: Data, Acknowledgement, Beacon and MAC Command. The Data frame (Figure 3) can carry up to 104 bytes of payload. The Acknowledgement frame is used by a re- ceiving station to “acknowledge” to the transmitting station that a data packet was received without error. The Beacon frame is used by stations that may be implement- ing significant power saving modes, or by Coordinator and Router devices that are attempting to establish networks. The MAC Command frame provides some unique abilities to send low-level com- mands from one node to another. Figure 4 demonstrates the timing involved in a data transaction between two devices. The sensor wakes up either on an event or at the end of an interval, checks the channel, transmits its mes- sage, awaits the acknowledgement, then may go back to sleep or first receive data intended for the node before going back to sleep. The 802.15.4 MAC medium access control layer contains over two dozen primitives that allow data transfer, both inbound and outbound, as well as man- agement by higher-level entities of the RF and PHY. The IEEE 802.15.4 specifica- tion uses a 64-bit unique address for every radio node. The 64-bit address is used in peer-to-peer communications, where no established network is available. How- ever, once in a network, the 64-bit address is traded for a 16-bit address to reduce packet overhead. There are two physical types of devices specified in 802.15.4, and three logical types. The two physical types are the Full Function Device (FFD) and the Reduced Function Device (RFD). While either de- vice may act as a sensor node, control node or composite device, only the FFD may perform routing tasks for a network. FFDs may, depending on their location in a network, have child devices for which the router performs routing functions. RFDs do not route, and therefore cannot have child devices. Figure 5 is a graphical repre- sentation of the connectivity practical in a ZigBee network using 802.15.4 devices. ZigBee Networking ZigBee networking is natively mesh- based. Cost-effective, simple radios Applications Application Framework Network/Security Layers MAC Layer PHY Layer ZigBee Certified Product ZigBee- Compliant Platform IEEE- Compliant Radio Application ZigBee Platform Stack Silicon Figure 2 ZigBee device construction. Figure 3 IEEE 802.15.4 Data frame. Octets: 2 1 4 to 20 n 2 MAC Sublayer Frame Control Data Sequence Number Address Information Data Payload FCS MHR MSDU MFR Octets: 4 1 1 5 + (4 to 20) + n PHY Layer Preamble Sequence Start of Frame Delimiter Frame Length MPDU SHR PHR PSDU 11 + (4 to 20) + n PPDU
TechnologyInContext 16 April 2006 cannot use high transmit power to ensure successful transfer of data. Instead, the network must be more clever—the most robust route between source and desti- nation may not be the obvious, shortest physical path route, but instead a route that requires other radios to “relay” the information. The ZigBee networking specifica- tion provides networking mechanisms that allow a developer to create star, tree and mesh network topologies, depending on network requirements. Once formed, a wireless network can be subject to in- terference, propagation changes, contin- ued growth, unintended usage and secu- rity issues. How does a ZigBee network respond to these factors? Wireless networks bring with them added flexibility in deployment and modification, but do not carry the generally assured connectivity that twin strands of copper wire provide. By no means does that make a wireless system less useful or robust. The wireless system architect must understand the types of environments in which the wireless net- work is expected to be used, the usage patterns and (at least) the most common failure modes. With this information, mit- igations may be crafted that improve the reliability and robustness to levels that are “good enough.” ZigBee networking (NWK) sits atop the IEEE RF/PHy/MAC and provides the required functionality to create and manage mesh networks. There are two types of ZigBee networks—a self-form- ing, self-healing network intended for environments where user intervention in the network is not expected nor intended; the other is designed for environments where there are persons that are net- work experts and regular configuration changes are expected. Networks physically larger than 2^16 nodes are broken into multiple sub-net- works, just like Internet addresses are di- vided into subdomains, partially for ease of use and also for added robustness and network capacity. In a live network pictured in Figure 6, the initial network address allocation created a default tree network, but quickly the network routing devices (1, 2, 5, 7, 8, 9) begin to learn additional routes be- tween themselves, creating a mesh net- work that may actually do the majority of the routing, depending on routing perfor- mance. For instance, the sensor 14 default route to the device 1 home security panel is 14>8>2>1, a total of 3 hops. However, there’s a shorter route 14>8>1, which probably has a higher reliability since it has one less hop to it. Once the mesh route is learned, it is probable that data from oc- cupancy sensor 14 will travel via the mesh route to the security panel. Developing the Product Creating the product first depends on how much of the ZigBee “functionality” is required. If the desire is to have a stan- dard application that will be broadly in- teroperable with other vendors’ products, the best choice is to go with the ZigBee Alliance-approved profiles and device descriptions. These product profiles have been completed for the Residential Auto- mation space, and will soon be available for the Commercial Building Automa- tion and Industrial Sensor spaces. Other market spaces, like Automated Meter Battery-Powered Sensor Mains-Powered Router Interval timer expires: Wake Up CCAx2 RX>TX TX TX>RX ACK RX RX Data Set Interval timer Sleep RX RX>TX ACK TX OPT: Pending ON TX Data 256 μs 192 μs ~650 μs 192 μs ~350 μsCheck-in only ~1640 μs Event and Get Data ~2300 μs ~650 μs Figure 4 IEEE 802.15.4 Timing and minimum latency ZigBee Coordinator ZigBee Router ZigBee End Device Figure 5 ZigBee/802.15.4 Mesh network and device types.
Now the world’s most desirable human interface can have time-critical responsiveness. W indows XP and our INtime RTOS run on the same platform, so no application is too fast for W indows. You’ll cut through timing jams and keep critical events under control. INtime’s robust stability and time-tested reliability handle hard real-time applications easily. The beauty of systems using INtime 3.0 is keeping all the advantages of a Windows environment without adding hardware cost or complexity. Speed your design cycle with power and grace. Using Microsoft ® Visual Studio® tools to develop and debug both Windows and INtime applications is easy and saves time. You’ll pass the competition with real authority. It pays to be prompt. Learn how the union of Windows and INtime really works, and how 25 years of practical innovation profits you. Call toll-free (877) 277-9189 or visit www.tenasys.com/intime 2004 Copyright © 2006 TenAsys Corporation. All rights reserved. TENASYS, INTIME, and IRMX are registered trademarks of TenAsys Corporation. Other trademarks and brand names are the property of their respective owners. INtime ® keeps Windows ® on time. 2005
TechnologyInContext 18 April 2006 Reading, are of interest to parties within the Alliance and thus may have profiles developed in the near future. First, a word on profiles: These are descriptions of specific applications for ZigBee technology, and a profile will con- tain within it descriptions of devices that are intended to be interoperable within that environment. Just because it uses Zig- Bee technology doesn’t mean that it was intended to be interoperable. An example of that might be the 100 hp, 3-phase mo- tor controller that’s used in an industrial automation space and the $20 peel-n-stick light switch used in Grandma’s den. While in concept, there’s no reason that the two devices couldn’t interoperate, it’s not ex- pected that they need to. However, the $20 light switch from company A and the $20 light switch from company B, both sold out of your local home improvement store, had better be able to quickly, easily and efficiently join your home’s ZigBee network and behave in a similar, predictable fashion. The pro- file defines the broad market space (Resi- dential Automation), while individual de- vice descriptions contained within (light switch, non-dimming) provide to the de- veloper the template for coding a device that is interoperable with other similar devices within the Residential Automa- tion space. Profiles are constructed by member companies that have an interest in that space. If the application can map to an ex- isting profile and device description, then product development can be very straight- forward. Alternatively, a product intended for a proprietary space or application can still take advantage of the ZigBee networking functionality without the in- tention of broader interoperability. It all Figure 6 Tree routes and mesh routes. Table 1 IEEE 802.15.4 frequency allocations and basic PHY parameters. Frequency Band (MHz) 868.3 902-928 2400-2483.5 # of Channels 1 10 16 Bandwidth (kHz) 600 2000 5000 Data Rate (kbps) 20 40 250 Symbol Rate (ksps) 20 40 62.5 Unlicensed Geographic Usage Europe Americas (approx) Worldwide Frequency Stability 40 ppm
TechnologyInContext April 2006 19 Ricoh Electronics, Inc. is a leader in manufacturing and developing high quality, long life embedded systems. We provide our customers with standard boxes, motherboards and chassis products for their embedded systems. These systems are manufactured in our vertically integrated manufacturing plant in Tustin, California. Our factories are ISO-9001 and ISO-14001 certified and RoHS compliant. We provide our customers with the following manufacturing services: Design for manufacturability Printed circuit board assembly Systems integrations and product assembly Metal and plastic parts design and fabrication Logistic support, including drop-shipping to your customers/end-users Supply chain management Ricoh Electronics, Inc. Embedded Products: Intel® embedded chipset architecture Customization of product and BIOS Qualified and tested board components One Ricoh Square 1100 Valencia Ave. Tustin, CA 92780, USA Phone: 714.566.6017 www.rei.ricoh.com TM Visit us at www.rei.ricoh.com by the Alliance in the Profile/Device Description document. Testing for simple devices like the light switch is quick—it should be in and out within a day or two of testing. When it successfully passes testing to the Alliance’s specification, the test house is authorized to provide a letter of certification, which the developer may next provide to the Alliance in exchange for authorization to use the ZigBee logo on the product. Once that authorization is received, the developer may go into large-scale production for that product, and the ZigBee logo imprinted on the product gives strong confidence to the consumer that this product, like others with the same logo for the same space, will interoperate successfully and simply. Freescale Semiconductor Austin, TX. (800) 521-6274. [www.freescale.com]. depends on what the developer and their market need. Assume that the application is for that “peel-n-stick” light switch, to be sold at one of the major home improve- ment chains. There, it’s best to start with a ZigBee Alliance-compliant platform, an intermediate product already validated as being compliant at the IEEE 802.15.4 level, with a compliance-tested ZigBee network stack, security toolbox and stack profile targeted to the developer’s applica- tion space. Starting with this compliant platform allows the developer to avoid the challenges of building a ZigBee network stack, integrating the security suite, and obtaining a much broader certification verification that is both more costly and time-consuming. And, there are at least a half-dozen manufacturers of ZigBee- compliant platforms available today, with more coming as time goes on. Once the selection of the ZigBee- compliant platform has been made, the developer can sit down with the Home Automation profile, check out the man- datory features of the device description for the “light switch, non-dimming,” and decide to implement strictly that or, in fact, add some extra functionality that is or may be expected by their customer. Once the design is done and the software coded and tested, the developer may want to do further interoperability testing using some store-bought “golden devices,” or bring the design instead to one of the Zig- Bee Alliance’s ZigFests, a quarter-annual event that allows them to test their product for interoperability at multiple levels, in an atmosphere of confidentiality. This important step validates the de- sign for the developer, gives them a strong indication of the product’s ability to in- teroperate with similar products in the space, and provides a strong assessment of the basic functionality and compliance of the product. Next, with demonstration of interoperability in hand, the developer may take their product to one of the two ZigBee Alliance approved test houses for certification testing. Once at the test house, the develop- er’s engineering sample product is sub- jected to a subset of IEEE 802.15.4 test- ing, some over the air measurements and compliance to the minimum func- tional requirements expected and defined
20 April 2006 High-Speed and Hybrid Backplanes VXS Processor Mesh Architecture: Powerful, Flexible, Compatible Although the VXS Processor Mesh architecture does not define any new backplane pin assignments beyond those already defined within the VITA 41.0 base specification, bandwidth capabilities exceed 112.5 Gbits/s of aggregate throughput within the processing mesh in a single chassis. V MEbus has morphed once again. One of the most promising devel- opments is VME Switched Serial (VXS), also known as VITA 41. Like many of today’s specifications, there are a host of subsidiary documents to support the platform, which is VITA 41.0. Other specifications define various signaling protocols—such as InfiniBand, RapidIO, Ethernet and PCI Express—all of which can utilize a single backplane physical architecture that is defined by the base document. The latest VXS innovation is the VXS Processor Mesh specification, VITA 41.7, developed by Elma Bustronic. This new backplane architecture, first demonstrated at Bus&Board 2006 in Long Beach, will provide a higher level of connectivity for VXS than has ever been previously consid- ered. Perhaps its major significance is the fact that it does not define any new slot me- chanics, connectors or channel definition. VXS defines within VITA 41.0 two new classes of cards: payload cards and switch cards. The payload card imple- ments a single new differential connec- tor in the P0/J0 position that exists on conventional VME64x cards today. The switch card defines a slot that is filled top to bottom with the new high-speed, dif- ferential MultiGig connectors. Standard Slots, Flexible Configurations Processor Mesh defines a set of five fully meshed switch card slots, with four bi-directional channels—a total of 32 dif- ferential pairs—between each slot and ev- ery other slot. This configuration became a reality when a VXS switch card ven- dor began discussing its application with Elma Bustronic. The two switch slots on a conventional VXS dual-star backplane are enough for most applications. However, in an especially challenging requirement, as many as five of these processor boards would probably be needed. In addition, a greater level of connectivity between each of these powerful cards was desirable. The challenge was how to integrate five switch cards into a larger VXS sys- tem in a useful way that would be flexible enough to support the widest range of other, similar applications. At the same time, the processing resources on those cards had to function at their highest capability. The re- sult became VXS Processor Mesh. The new backplane topology inte- grates conventional VXS switch cards in a mesh configuration. Therefore, the switch cards are no longer connected directly to any payload cards, but only to other switch cards. The connection paths between each and every one of the four mesh slots consist of four direct, unswitched channels, which together offer a bi-directional 40 Gbit/s path. They could also be used as 32 differ- ential pairs in a single 80 Gbit/s unidirec- tional pipe. This meshed section is for special pro- cesses and is in addition to the two con- ventional dual-star fabric slots that are still required to support the “A” and “B” fabric connections to the payload slot in a system (Figure 1). With this new architecture, VXS back- planes are no longer limited to a single pair of fabric switches. Most importantly, the pay- load cards and switch cards in VXS Proces- sor Mesh can be the exact same cards that are used in the classic dual-star VXS systems. VXS supports the continued use of ex- isting VME64x cards. This is particularly important when special cards have been de- veloped by end customers to serve as a cus- tom interface to a special type of sensor or output device. For example, if those cards used a 2 mm HM connector in the P0 position, it can now be replaced with a single differential Mul- tiGig P0 connector that supports 20 times by Michael Munroe Elma Bustronic SolutionsEngineering Get Connected with companies mentioned in this article. www.rtcmagazine.com/getconnected Get Connected with companies mentioned in this article. www.rtcmagazine.com/getconnected End of Article exploration er your goal eak directly al page, the t resource. chnology, and products panies providing solutions now ration into products, technologies and companies. Whether your goal is to research the latest lication Engineer, or jump to a company's technical page, the goal of Get Connected is to put you ice you require for whatever type of technology, ies and products you are searching for.
April 2006 21 SolutionsEngineering the bandwidth of the existing 2 mm HM center connector. Both Processor Mesh and Payload Mesh VXS backplanes have been produced with one or more slots equipped with the legacy 2 mm HM center connector, in order to accommodate existing VME64x cards that do not currently justify being re- designed (Figure 2). FPGAs Prefer Direct Connections Another consideration is the fact that many high-performance VXS cards are FPGA-based. FPGAs from Xilinx, Al- tera and others are most effective when used in point-to-point topologies. FPGA- based designs require less code and deliver more performance when used with direct, streaming serial protocols such as Aurora and SerialLite. Although the VXS standard was designed to support a switched fabric topology, VXS backplanes will not always be used for this purpose. The core VXS document, VITA 41.0, is written to support a switched topology that might comprise 18 payload cards and two fabric switches. Typically, a dual-star back- plane links any two payload cards through one of the two fabric switches. A single- star architecture, or the same dual-star architecture, supports point-to-point appli- cations perfectly when the processors are located on cards in the switch slots. When each payload is designed to communicate only with the processing card, there is no need for a conventional fabric switch. But what if an application will re- quire more processing cards, for instance, three, four or even five? This is where VITA 41.7 comes in. It enhances the VXS platform by supporting an array of up to five processing cards in an arrangement that is ideal for high-bandwidth, point-to- point signaling. Additional features of the topology allow this specialized process- ing bus segment to be integrated with the rest of the backplane in a very flexible and scalable manner. The MultiGig connector is used in po- sitions J1 through J5 in a Processor Mesh backplane. Connectors J2, J3, J4 and J5 provide enough channels to allow four channels of connectivity between each and every card in the mesh. Of the remain- ing channels in those four connectors, two channels are allocated to the center fabric channels and two channels are reserved for future I/O uses. The J1 backplane con- nector in the conventional switched slots, as well as in the Processor Mesh switched slots, provides all of the system signals for management and other functions. J1 also provides undefined pins. Each 16-row MultiGig differential backplane connector in VXS switch slots supports six full channels. That means that the four fabric connectors—J2, J3, J4 and J5—can support a total of 24 channels of point-to-point connectivity. In addition, there is a J1 connector that supports a wide array of slower system signals. The power connector is separate and provides A0K0 Fabric A Fabric B Sys RFU Sys J1 J2 J0 Fabric A Fabric B Meshed Switch Blade Slots PWR1 PWR1 PWR1 PWR1 PWR1 PWR1PWR1PWR1 PWR1 PWR1 PWR1 PWR1 With or without VME 64x Payload Slots Switch Slots Meshed Switch Blade Slots Required Power RFU System A1, K1 Fabric A Fabric B RFU RFU 6 channels each J2, J3, J4, J5 Optional Power A2, K2 J1 J2 J3 J4 J5 J1 J2 J3 J4 J5 J1 J2 J3 J4 J5 J1 J2 J3 J4 J5 J1 J2 J3 J4 J5 J1 J2 J3 J4 J5 J1 J2 J3 J4 J5 V S V S V S V S Figure 1 VXS Processor Mesh backplane topology integrates conventional VXS switch cards in a mesh configuration. In this example, on the left are payload VXS slots, with or without legacy VME64x slots. In the center are the A and B fabric slots, and on the right are the meshed switch blade slots.
SolutionsEngineering 22 April 2006 30 amps of +5 VDC for a total of 150W. At present, there appears to be no ar- chitecture that has more data transport con- nectivity than that provided by VITA 41.7. VITA 46, not yet released, does not provide for more channels, nor does it define a stan- dard mesh implementation. Both PCI Express and CompactPCI Express can support a max- imum of 16x bi-directional links. AdvancedTCA, for example, does de- fine a 16-slot mesh backplane with a single 10 Gbit/s channel between each of the 16 cards. However, the smallest redundant meshed application that is defined is a five- slot mesh, which can also offer four chan- nels of connectivity between each of those meshed slots. This is exactly what VITA 41.7 now provides. Figure 2 Shown from left to right are a 20-slot dual-star, a five-slot single-star, a five-slot switchless mesh with three slots meshed over the payload slots and two legacy VME64x slots, and a 12-slot Processor Mesh. The VXS Processor Mesh backplane has four meshed switch slots, three payload slots, one fabric switch slot and two legacy VME64x slots. 5 Meshed Fabric Slots 8 V41 Processor 9 V41 Processor 10 V41 Processor 11 V41 Processor 12 V41 Processor The 5 Processor blade slots are on 5HP pitch PP18 PP17 PP16 12-PP04 12-PP08 12-PP12 12-PP16 11-PP16 PP15 12-PP03 12-PP07 12-PP11 12_PP15 12-PP15 PP14 12-PP02 12-PP06 12-PP10 12-PP14 11-PP14 PP13 12-PP01 12-PP05 12-PP09 12-PP13 11-PP13 PP12 11-PP04 11-PP08 11-PP12 10-PP12 10-PP16 PP11 11-PP03 11-PP07 11-PP11 10-PP11 10-PP15 PP10 11-PP02 11-PP06 11-PP10 10-PP10 10-PP14 PP09 11-PP01 11-PP05 11-PP09 10-PP09 10-PP13 PP08 10-PP04 10-PP08 9-PP08 9-PP12 9-PP16 PP07 10-PP03 10-PP07 9-PP07 9-PP11 9-PP15 PP06 10-PP02 10-PP06 9-PP06 9-PP10 9-PP14 PP05 10-PP01 10-PP05 9-PP05 9-PP09 9-PP13 PP04 9-PP04 8-PP04 8-PP08 8-PP12 8-PP16 Channel 4 PP03 9-PP03 8-PP03 8-PP07 8-PP11 8-PP15 Channel 3 PP02 9-PP02 8-PP02 8-PP06 8-PP10 8-PP14 Channel 2 PP01 9-PP01 8-PP01 8-PP05 8-PP09 8-PP13 Channel 1 SP04 6-SP02 6-SP04 6-PP02 6-PP04 6-PP06 Channel I/O SP03 6-SP01 6-SP03 6-PP01 6-PP03 6-PP05 Channel I/O SP02 7-PP12 7-PP13 7-PP14 7-PP15 7-PP16 Fabric A SP01 7-PP05 7-PP06 7-PP07 7-SP01 7-SP02 Fabric B Figure 3 Five fully meshed slots include two fabric channels and two I/0 channels. each pair= 3.12 Gb/s each channel=10 Gb/s 1 channel= 4 transmit pairs 4 receive pairs Redundant Mesh 4 Channels from slot to slot
SolutionsEngineering April 2006 23 computation. The results of that operation are then passed on to another card where a different processing algorithm is applied. This may be continued until the data has passed through each of the five cards. The final results can then be exported by means of the central fabric channels. If the system vendor develops a new card that is more highly integrated, this card can replace two of the cards that were Figure 4 A typical, 16-row MultiGig connector supports six 10 Gbit/s channels. Row A Row B Row C Row D Row E Row F Row G Row H Row I 1 Channel PP9 PP9 Receive 0 PP9 Transmit 0 PP5 Transmit 0 Channel PP5 2 PP9 Receive 1 PP1 Transmit 1 PP5 Transmit 1 3 PP9 Receive 2 PP9 Transmit 2 PP5 Transmit 2 4 PP9 Receive 3 PP9 Transmit 3 PP5 Transmit 3 5 Channel PP7 PP7 Receive 0 PP7 Transmit 0 PP5 Receive 0 6 PP7 Receive 1 PP7 Transmit 1 PP5 Receive 1 7 PP7 Receive 2 PP7 Transmit 2 PP5 Receive 2 8 PP7 Receive 3 PP7 Transmit 3 PP5 Receive 3 9 Channel PP3 PP3 Receive 0 PP3 Transmit 0 SP1 Transmit 0 Channel SP1 10 PP3 Receive 1 PP3 Transmit 1 SP1 Transmit 1 11 PP3 Receive 2 PP3 Transmit 2 SP1 Transmit 2 12 PP3 Receive 3 PP3 Transmit 3 SP1 Transmit 3 13 Channel PP1 PP1 Receive 0 PP1 Transmit 0 SP1 Receive 0 14 PP1 Receive 1 PP1 Transmit 1 SP1 Receive 1 15 PP1 Receive 2 PP1 Transmit 2 SP1 Receive 2 16 PP1 Receive 3 PP1 Transmit 3 SP1 Receive 3 A Defined Platform Ensures Multi-Vendor Interoperability The fact that the fabric slot has a fixed channel definition across all VXS subsidiary specifications—including the new VXS Pro- cessor Mesh architecture—is important to the development of VXS infrastructure. The efforts at maintaining compatibility in the VME standard ensured that a steady stream of new products would continue to be pro- duced by a diverse community of card ven- dors. In the same way, the fixed slot defini- tions in VXS mean that vendors can be sure that the cards they produce for one applica- tion can be used in any other VXS backplane being developed. In a typical VXS Processor Mesh backplane, the center fabric channels that are part of the basic dual-star architecture are carried forward onto fixed locations on each of the five processor mesh slots. This is to ensure application scalability. VXS Processor Mesh is Scalable One architecture that might be imple- mented within the meshed processor slots is a pipeline. In a pipeline topology, data is delivered to the first card in a series for
SolutionsEngineering 24 April 2006 backplane with a high number of slots is available off the shelf, such a backplane can be used if there is physical space to accom- modate the unneeded slots. VXS is Future Proof Not every application will need all of the connectivity that the Processor Mesh architecture can provide. After all, most typical VXS applications do not require more processing than can be squeezed onto the two conventional VXS fabric slots. However, the development of VXS Pro- cessor Mesh is a significant boost for VXS. With four 16x redundant mesh channels be- tween each slot, no other architectures on the horizon have more connectivity. Pro- viding both backward compatibility and a forward performance path, VXS Processor Mesh offers a great deal of flexibility. Since VXS Processor Mesh defines a standard slot and at least three different back- plane architectures, there will most likely be a large number of interoperable products avail- able during the next year. For these reasons, VXS Processor Mesh has brought a higher level of performance to VXS, effectively fu- ture-proofing the entire VXS product line. What Comes Next With the addition of the Switchless Pay- load architecture, and now the Processor Mesh architecture, VXS implementers can expect to see a number of additional back- plane designs. For instance, it has been clearly demonstrated that the three-slot switchless payload card mesh is not limited to a single set of three cards. Instead, it is quite possible to array as many as seven sets of these three slot meshes along a single VME backplane. The same is true for VXS Processor Mesh. Although it is difficult to imagine an application today that would need such processing power, two or even three 5-slot mesh segments could be laid out on a sin- gle VXS backplane. In this case, I/O would probably have to come in via the front panel or be concentrated at the six remain- ing payload cards. Elma Bustronic Fremont, CA. (510) 490-7388. [www.elmabustronic.com]. previously part of the pipeline. In some other architectures it might not be possible to have an unpopulated backplane slot, because there might be no alternate channel where data could be exported out of the pipeline. This would be the case if the designers did not provide identical support to each slot. In another hypothetical situation, a system might be developed with the same set of five cards. In this scenario, the al- gorithm implemented on one of the cards might not be useful for a new type of data being processed. Because VXS Processor Mesh pro- vides the two fabric channels that connect each of the five meshed slots to the rest of the system, and because there are ad- ditional RFU pins that could be also used for I/O, the meshed switch slots are very flexible. Any card configuration would be supported whether it required only a single slot or the entire five slots. This emphasis on standard slot pin- outs for all switch card slots makes it pos- sible for system integrators and backplane vendors to stock only a relatively small selection of all the different possible VXS backplane designs. Even if only a large www.rtecc.com at the RTECC Dallas Richardson Civic Center Join us at the Real-Time & Embedded Computing Conference (RTECC). Learn more about the latest VXS Processor Mesh specification, VITA 41.7, developed by Elma Bustronic. And see why this new backplane architecture will provide a higher level of connectivity for VXS than has ever been previously considered. Talk to our experts about the significance that it does not define any new slot mechanics, connectors or channel definition. Go to www.rtecc.com/dallas and pre-register for this complimentary conference. We’ll see you on Tuesday, June 6, 2006 ! June 6, 2006 ELMA See rtecc_elma_april.indd 1 4/11/06 11:10:42 AM
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SolutionsEngineering 26 April 2006 High-Speed and Hybrid Backplanes Functionality and Design of AdvancedTCA Backplanes AdvancedTCA backplane architecture provides scalability and balances cost with performance. Its tight construction guidelines, implemented to guarantee interoperability, require close attention to certain design parameters. by Andreas Lenkisch Schroff The backplane is the heart of data trans- fer on the chassis. How good and fast its pulse or heartbeat is represents the performance of the entire system. In order to avoid placing architectural limits on per- formance, the PICMG specifications group has approached development of an open backplane specification, AdvancedTCA (ATCA), from a completely new, but not unusual, direction (Figure 1). No More Parallel Bus Open protocols, upgradability and scalability were set as targets when the ATCA architecture was originally de- fined. These factors will ensure longev- ity, versatile application possibilities and cost effectiveness. The architecture is logically supported by serial, packet-ori- ented transfer protocols and physically by point-to-point interconnects. A parallel bus is no longer used for data transfer. By eliminating the parallel bus and using di- rect point-to-point interconnects, the high- est possible multi-gigabit/s transfer rates can be achieved. The maximum performance of con- ventional parallel 32-bit or 64-bit buses is limited by two factors. First, they are limited by a technically unavoidable skew, or time lapse, between individual signals. Second, they are limited by the multidrop/ multipoint bus structure of the backplane itself. Each slot acts like a lowpass filter and removes the sharp edge of the signals. Point-to-point connections do not have this undesirable behavior. A network on a backplane with its point-to-point connections is universally and simply defined. In the PICMG 3.0 basic specification, various topologies and physi- cal properties are determined. The use of connections for specific protocols is de- scribed in sub-specifications, the so-called “dot specs,” such as PICMG 3.1, PICMG 3.2 and PICMG 3.3. This subdivision of the specification is highly advantageous, since it allows for ad- ditional sub-specifications to be made over time. To date, specifications for Ethernet (3.1), InfiniBand (3.2), StarFabric (3.3), PCI Express (3.4) and Advanced Switching In- terconnect (3.5) have been defined. These protocols can be mixed in a single chassis. If a board is inserted into the wrong slot, electronic keying will disable the incompat- ible ports and eliminate physical damage from incompatible line drivers. Different Topologies Star and mesh backplane topologies are described in the ATCA specification. Depending on the application, other back- plane topologies may be desirable. A “rep- licated mesh” topology increases the data transfer rate between slots without increas- ing the speed of the individual connections. A “daisy chain” or ring topology is com- monly used outside of the telecommunica- tions area. In this topology, each slot is con- nected with the neighboring slot or to the neighbor two slots down. Get Connected with companies mentioned in this Get Connected with companies mentioned in this article. www.rtcmagazine.com/getconnected Get Connected with companies and products featured in this section. www.rtcmagazine.com/getconnected Ad Index End of ArticleProducts Get Connected with technology and companies providing solutions now Get Connected is a new resource for further exploration into products, technologies and companies. Whether your goal is to research the latest datasheet from a company, speak directly with an Application Engineer, or jump to a company's technical page, the goal of Get Connected is to put you in touch with the right resource. Whichever level of service you require for whatever type of technology, Get Connected will help you connect with the companies and products you are searching for. www.rtcmagazine.com/getconnected Get Connected with technology and companies providing solutions now Get Connected is a new resource for further exploration into products, technologies and companies. Whether your goal is to research datasheet from a company, speak directly with an Application Engineer, or jump to a company's technical page, the goal of Get Connec in touch with the right resource. Whichever level of service you require for whatever type of technology, Get Connected will help you connect with the companies and products you are searching for. www.rtcmagazine.com/getconnected Figure 1 14-Slot AdvancedTCA backplane according to PICMG 3.0.
SolutionsEngineering 28 April 2006 If a special backplane topology is chosen for a specific application stan- dard ATCA boards can still be used. The backplane interface is a packet-oriented switched fabric protocol and the ports on the backplane are always in the same place. Therefore, chassis for special appli- cations can be configured cost effectively with existing hardware on an ATCA base. Only a small portion of the overall design must be developed anew. This is the great advantage of ATCA: flexibility that was incorporated into the specification from the beginning. During the development of the ATCA specification the working group decided to keep the data transfer and control planes separate. The protocol diversity and open- ness is designed for the data transfer plane, the fabric interface. For compatibility rea- sons, 10/100/1000BaseT Ethernet was deter- mined to be the best choice for the control plane, the base interface. A redundant, or dual-star, topology was defined. By restrict- ing the design choices for the base interface, compatibility is guaranteed (Figure 2). Scalability as Cost Restriction The fabric interconnect between ATCA backplane slots is called a channel. Each channel can contain one, two or four ports, or lanes. Each port consists of a differential transmit and receive pair, that is, Tx+, Tx- and Rx+, Rx-. This is one example of how scal- ability was implemented in ATCA from the start. Less performance will also cost less, on the board as well as on the backplane. Hav- ing scalable computer architectures based on open specifications was not the case until now. CompactPCI is one example. Tight construction guidelines were de- fined for the ATCA backplane in order to guarantee interoperability among different manufacturers. A unified connection struc- ture, as well as channels and ports assigned to designated connectors and pins, are im- portant criteria for interoperability. How- ever, they are no longer sufficient for multi- gigabit transfers. Not only should the signals be transferred at state-of-the-art speeds, but the system should also be upgradable to make investments “future proof.” This is primarily an issue of cost, which was also taken into account dur- ing the draft of the ATCA specification. Today’s protocols are considered to be fast with signal speeds of approximately 3 Gbits/s. For example, 10 Gigabit Ethernet on an ATCA backplane uses four differen- tial pairs running at 3.125 Gbits/s on each pair. In the coming years we can expect to see transfer speeds of 5 to 6 Gbits/s or even more. These faster rates will be expected to run on the same infrastructure Switch Design with Restricted Freedom In the past, high-speed designs were proprietary. Individual elements of the data transfer, such as the backplane or the transceiver, could be closely coordinated with each other. In order to achieve cor- rect operation under all conditions in the field, the system architect had full control over all elements and could decide on suit- able compromises. Since ATCA is an open specification, interoperability between the products from various manufacturers worldwide must not only be guaranteed to- day, but also for future upgrades. Therefore, it has become necessary to define, and adhere to, an interface that is much more constrained than would possi- bly be required for a proprietary solution. Zone 1 (Power, Shelf Mgmt) Zone 2 (High-Speed Data Transport) P20 P21 P22 P23 P24 J10 1 2 3 4 5 Logical Slot Mechanical Keying & Guiding Telephony Clocks (6 LVDS pairs 130 Ohm) Update Port Interface (10 diff pairs between (adjacent) slots) Fabric Interface (data plane) 1 Channel between Slots 1, 2 or 4 ports per Channel; port:: 2 diff. pairs Tx/Rx Base Interface (control plane) 1 Ethernet 10/100/1000 Base T Low speed Shelf Management (IPMI) Ring & Metallic Test Lines Dual Independent Power (-48V) ATCA Backplane Fuctional Blocks Figure 2 Distribution of specific functions to the ATCA backplane connectors. L/4 Signal splits into two paths. One enters the trace directly. The other travels along the via, becomes reflected at the bottom and then enters the trace. Signal is injected from the connector pin into the backplane. Stub or L/4 Resonances the signal disappears Figure 3 Stub resonances cause the signal to be cancelled at resonance frequency.
SolutionsEngineering April 2006 29 In an open specification, there will be less design freedom than there is in a completely customized solution. For the time being, this lack of design freedom primarily affects signal skew, the transmission time difference between vari- ous signals. The skew on the backplane can be divided into several groups: skew between each leg of a differential pair, skew between different lanes within a channel and skew within different pairs in the base interface. The tightest condition for skew is <3.4 picoseconds (ps) between signals on each leg of a differential pair. The transmission dif- ference between pairs within a fabric chan- nel cannot be more than 17 ps, or more than 60 ps for pairs within the base interface. To make these times understandable, a time window can be imagined in which light would travel 1 mm or 5 mm in air, or a sig- nal would travel 0.5 mm or 2.5 mm through a printed circuit board. To establish a skew of less than the maximum specified value, the difference in the length of the traces within the backplane must be smaller than the stated distance. To make traces of equal length is the right starting point, but it is not sufficient to guarantee a skew less than the maximum specified value. Other influences can significantly af- fect the speed of the signals, maybe more than the difference in conductor length. The skew between signals at the end of a trace is dramatically influenced by the surrounding dielectric. This skew is caused by the sig- nal traveling through a glass-epoxy-based dielectric, the PCB, which is not homoge- neous. In the past, the signal traces were wider than the woven glass bundles in the PCB. This averaged the signal velocity so that skew was minimal. The narrow signal traces in a PCB are now nearly the same size as the woven glass bundles. A signal that is under a glass bundle will travel at a different speed than one that is not under a glass bundle. Another effect influencing or contrib- uting to signal skew, even when the traces are of equal length, is signal delay caused by distortion of the electrical field as the signal goes through an area that contains vias or pads. Vias cause additional para- sitic capacitance and change the speed of the signal. It has also been established that We design solutions. You define success. Mercury customers span multiple industries and face unique computing challenges –whether improving yields for semiconductor wafer inspection, increasing throughput in medical imaging, rendering high-quality animation within a defined budget, or packing enormous processing capacity in deployed ground vehicles. Why are we so driven to tackle these difficult computing problems? Because your challenges drive our innovation. Our new 1U Dual Cell-Based Server significantly improves performance for computationally intensive HPC applications in medical, industrial, defense, seismic, telecommunications, and other industries. Contact us to learn how our products and services can optimize your challenging applications. Let us design an innovative solution for you. www.mc.com/rtc4 | 866-627-6951 TM mcs_rtc_ad_4-06.qxp 3/31/2006 2:07 PM Page 1
SolutionsEngineering 30 April 2006 the signal speed near a via is not the same as when it is measured along a conductor in the layer. These effects can only be captured by three-dimensional field simulation. Using a 3D field solver will help to establish design rules that account for the vias. Vias also play a big role from another perspective. Vias can form a T-shaped branch in the circuit, called a stub (Figure 3). If a sig- nal is transmitted into a via from one of the top layers and then exits the via near the top layer, the signal will divide. Some of the en- ergy goes into the output signal trace near the top layer and another part of the signal goes toward the end of the via. There, the signal is reflected and then it, too, feeds into the out- put signal conductor. This problem is most apparent when the effective length of the via (stub) is 25% of the signal wavelength in the backplane (Lambda/4 Resonance). When there is resonance in the via, there is phase distortion between the two parts of the signal. This phase shift can partially obliterate the output signal. At frequencies where the phase distortion is 180°, total obliteration of the signal can oc- cur. With transfer rates of up to 1 Gbit/s, vias with lengths of less than 12 mm—the thickness of the backplane—do not have a negative influence on signal integrity and will not cause significant signal distortion or obliteration. At 3 Gbits/s, the via can only be 4 mm long, and at 6 Gbits/s it should be a maxi- mum of 2 mm long. These are the lengths that can be tolerated without the signal be- ing degraded dramatically. If the backplane is thicker because of a higher layer count, backdrilling—a manufacturing process that removes the unused part of the via—can re- duce effective via length. Mutual Dependencies A further prerequisite of the ATCA specification for sufficient interoperability is a low amount of signal crosstalk. Dif- ferential signal pairs should not be closer than the minimum distance determined by the design rules. This prevents a reduction in signal quality in terms of increased jitter and a reduced eye opening (a signal display on communications test equipment). In practice, these demands can only be fulfilled when a single differential pair is routed between two connector vias. The layer count is determined by this rule. This means that for a “full mesh” backplane, in which each of the 14 slots is directly con- nected to each of the other slots, a total of 30 to 34 layers is required. If a design allowed for two connector pairs between vias, the number of layers could be reduced by 50%. The thickness of the backplane PCB would also be reduced by 50%, which, in turn, would require shorter vias. But crosstalk would increase to approximately 5%, considerably exceed- ing the maximum of 0.2%. If a system ar- chitect has full control over all components of the signal path and can evaluate the con- sequences, this routing scheme can clearly be an option to lower costs. The interactions of the individual sig- nal integrity properties—such as imped- ance, crosstalk, stub resonances and skew— influence each other in turn. The dielectric spacing of the individual layers, conductor width, distance of the traces within a dif- ferential pair and from pair to pair, trace routing in relation to vias and pads, and length adjustment strategy cannot be looked at individually. In particular, one parameter cannot be optimized without considering all of the others, due to their mutual dependen- cies. Simulation of various scenarios is very helpful in order to make the right decision for the optimum design and minimum cost. A wide-opened eye pattern (Figure 4) for higher speeds is also the result of proper weighting of all design parameters. Schroff Straubenhardt, Germany. +49 7082 794 674. [www.schroff.de]. 400mV 300mV 200mV 100mV 0mV -100mV -200mV -300mV -400mV 0.0 UI 0.2 UI 0.4 UI 0.6 UI 0.8 UI 1.0 UI Bit Pattern: PRBS Bit Pattern: PRBS Pattern Length: Rise Time: 50 ps Rise Time: 25 ps 2^7-1 Data Rate: 3.125 Gbps Data Rate: 7.500 Gbps Pair: 01P21_AB07-10P23_CD03 Pair: 01P21_AB07-10P23_CD03 Trace Length: 170, 1mm Eye Pattern @ 3.125 & 7.500 Gbps vs. XAUI spec Figure 4 Eye pattern at 3.125 Gbits/s and 7.5 Gbits/s on an ATCA backplane.
All trademarks are the property of their respective companies.Manufactured in Wixom, Michigan, USA A N A L O G I / O D I G I T A L I / O S E R I A L I / O F P G A C O U N T E R / T I M E R Q U A D R A T U R E Call us or visit our website today — for proven solutions in VME, PCI, CompactPCI, Industry Pack, and PMC. If you need dependable I/O, Acromag has your board. With more than 45 years of I/O experience and an unmatched selection of Industry Packs and I/O boards, Acromag is the one to trust.Our boards deliver uncompro- mising performance supported by time-saving software tools and cost-cutting high channel density—to ensure your projects stay on schedule and within budget. Industrial-strength designs with extended temperature ranges make Acromag I/O ideal for COTS and manufactur- ing applications.And with actively managed product life cycles, you’re ensured of long-term availability. Count on us for PMC, too. Our newest boards deliver impressive performance and outstanding value to PMC, PCI, and CompactPCI formats. Whatever your I/O need, Acromag has an I/O answer— depend on it. www.acromag.com/dependable.cfm 800-881-0268 or 248-624-1541
IndustryInsight CompactPCI and Switched Fabrics A dvanced Switching Interface (ASI) is an extension to PCIe that allows CPU-to-CPU communication and dynamic I/O mapping to work on top of the basic PCIe functionality. For multi- CPU systems, this provides a unification of the CPU-to-CPU communications bus and the I/O bus structure. This unifica- tion provides dramatic improvements in performance, system cost and fault tol- erance. With CompactPCIe, ASI bridge and switch components becoming avail- able in 2006, new systems that incorpo- rate ASI within CompactPCIe are sud- denly within reach. CompactPCI was developed in 1996 as a standard bus structure that combined the cost-effective PC bus architecture (PCI) with the popular Eurocard indus- trial board form-factor. This combination quickly became the world’s most popular bus structure for industrial, communica- tions, military and test systems where PCI is used in a rugged form-factor. In 2005, the PICMG standards body defined a new CompactPCI specification that incorpo- rates the new PCI Express (PCIe) bus in place of the original PCI bus. The CompactPCIe specification re- placed the P1 and P2 connectors with four connectors that provide the new PCIe bus as well as enhanced power capabilities to each board (Figure 1). The bottom con- nector provides high current connections for incoming power; the second and third connectors provide the PCIe differential pairs for multiple PCIe buses to be routed Get Connected with companies mentioned in this www.rtcmagazine.com/getconnected Get Connected with companies mentioned in this article. www.rtcmagazine.com/getconnected Get Connected with companies and products featured in this section. www.rtcmagazine.com/getconnected Ad Index End of ArticleProducts Get Connected with technology and companies providing solutions now Get Connected is a new resource for further exploration into products, technologies and companies. Whether your goal is to research the latest datasheet from a company, speak directly with an Application Engineer, or jump to a company's technical page, the goal of Get Connected is to put you in touch with the right resource. Whichever level of service you require for whatever type of technology, Get Connected will help you connect with the companies and products you are searching for. www.rtcmagazine.com/getconnected Get Connected with technology and companies providing solutions now Get Connected is a new resource for further exploration into products, technologies and companies. Whether your goal is to research datasheet from a company, speak directly with an Application Engineer, or jump to a company's technical page, the goal of Get Connec in touch with the right resource. Whichever level of service you require for whatever type of technology, Get Connected will help you connect with the companies and products you are searching for. www.rtcmagazine.com/getconnected by Steve Cooper One Stop Systems Advanced Switching can be used within CompactPCIe to allow multiple CPU boards and dynamically mapped I/O in high- performance, network topologies. Advanced Switching on CompactPCI Express Figure 1 New connectors and pin outs enhance CompactPCI boards to incorporate PCIe functionality and performance.
April 2006 33 IndustryInsight from each board to the backplane. The top connector provides specialized I/O sig- nals for user I/O or for PXI extensions for instrumentation. Since PCIe provides point-to-point connections, a switch is needed to con- nect the CPU to multiple I/O slots. Within the basic PCIe architecture a single CPU board is connected through a switch to multiple I/O boards (Figure 2a). ASI within CompactPCIe Advanced Switching Interface is a protocol that resides on top of the basic PCIe packets and adds additional routing information to each packet. This extra pro- tocol allows the PCIe topology to be ex- tended to support full network topologies that include multiple CPUs and dynami- cally mapable I/O, as shown in Figure 2b. PCIe I/O boards can continue to be used unchanged. This is accomplished by mapping each I/O function to an indi- vidual CPU board. I/O board mapping is dynamic, initially being set during system initialization, but later being changed due to hot-swap events or CPU board failures that require re-mapping. CPU boards need to have their PCIe bus signals converted to ASI-compli- ant signals before they can communicate within the network topology. This is ac- complished by sending each PCIe bus from the CPU through a PCIe-to-ASI bridge component. The specifications al- low this component to be placed on the CPU board or on the switch board. If the bridge component is placed on the switch board, then off-the-shelf CPU boards can be used unchanged within a tree or a net- work topology. In this case, the only el- ement that changes between the tree and network topology is the switch board. CompactPCI has built in flexibility in that its P3, P4 and P5 connectors are available for user defined rear I/O or sec- ondary buses or interconnects. Several uses for these connectors have themselves become standardized. One of the most popular of these is PICMG 2.16, which defines how 1 Gbit Ethernet can be routed through the P3 connectors to a special 2.16 switch slot. This mechanism allows multiple CPU boards to intercommuni- cate via the Ethernet in a network topol- ogy. “Split backplane” solutions have ex- tended this concept to allow multiple CPU domains (isolated CPU and I/O slots) to be integrated within a single system, with the CPU boards connected by Ethernet routed via 2.16. ASI as an Upgrade Path for 2.16 Systems ASI within CompactPCIe provides a particularly attractive upgrade path to 2.16-based systems. The advantages of ASI include 10x higher performance, lower costs and dynamic I/O mapping. A basic comparison between ASI and 2.16 solutions is shown in Table 1. ASI performance depends on the lane width of the underlying PCIe buses. Typical systems will include two independent x4 PCIe bus interfaces from each CPU board. Each of these interfaces operates at 10 Gbits/s. Higher performance is achievable by boards that utilize x8 or x16 interfaces, or from the move to Gen 2 timing, which is expected to become available in late 2007. Lower costs result from the combi- nation of two buses (PCI and Ethernet in 2.16) into one PCIe bus that performs both functions. CPU boards don’t need to drive the extra Ethernet ports into the backplane, and an expensive 2.16 switch board is eliminated. The CompactPCIe with ASI solution does require its own switch board, but this function provides both the I/O board fan-out and multipro- cessor switching functions. Dynamic I/O mapping allows any PCIe I/O function to be mapped to any CPU board, with the mapping change- able on-the-fly. This capability provides greater hardware configuration flexibil- ity and enhanced fault tolerance. If a CPU board in the network fails, a dif- ferent CPU board can be re-mapped to take over control of the I/O boards. This type of capability doesn’t exist within 2.16 systems. In those systems, if the controlling CPU board goes down, all the I/O associated with that CPU also goes down. CPU I/O I/O I/O I/O I/O I/O Switch CPU CPU CPU a b Figure 2 a) Tree architecture for CompactPCIe, b) Network architecture for CompactPCIe with ASI. CompactPCIe supports both architectures, with CPU and I/O boards used unchanged. CPCI with 2.16 CPCIe with ASI CPU-to-CPU Bus Ethernet CPCIe Performance 1Gb/s 10 Gb/s (x4) CPU-to-I/O Bus CPCI CPCIe Performance 132 MB/s 1 GB/s (x4) I/O Mapping Static Dynamic Table 1 Comparison of CompactPCIe with ASI versus PICMG 2.16.
IndustryInsight 34 April 2006 One of the key elements of an ASI system is the network resource manager software. This software runs on one (or multiple) CPU within the ASI network and initializes and manages the network devices. Some of the functions provided by this software include: • Network discovery, initialization and I/O mapping – The resource manager probes the entire network dis- covering the overall topology and each con- nected end-point. The var- ious bridge and switch components are initialized and the I/O end-points are mapped to particular CPUs. • Communication of network configura- tion—The resource manager commu- nicates the network topology and I/O mappings to all the other CPUs in the network. • Monitoring of network configura- tion changes – The resource manager continually monitors the network and determines any changes that occur due to elements failing or being inserted or removed. • Re-mapping and communication of network configuration changes – All network changes are communicated to the other CPUs within the network. The resource manager also processes requests for I/O mapping changes. ASI Networking outside the Box ASI networks can exist both within a CompactPCIe enclosure as well as out- side. The PCI-SIG is nearing completion of a standard cable specification that al- lows PCIe to be routed over cable at full bandwidth (10 Gbits/s for x4 cable). Stan- dard products for interfacing to this new cable are becoming available, including host interface boards, cables and switches (Figure 4). In the same way that standard Com- pactPCIe CPU and I/O boards can be used as is within either a basic PCIe or a CompactPCIe with ASI system, so too can standard PCs and PCIe I/O end- point systems be used within a cabled ASI network system. The CPU elements do need to go through a bridge compo- nent, which will typically be included on the cable interface add-in card. The switch box will need to be based on an ASI-compatible switch chip, and the network resource manager software will need to operate on at least one CPU el- ement within the network. These cable interface products for ASI are also be- coming available in 2006, and will fur- ther extend the value of ASI within a CompactPCIe system. ASI features added to CompactPCIe enable high-performance multi-CPU so- lutions with dynamic I/O mapping. These capabilities enable designers to build more powerful solutions with higher levels of fault tolerance than ever before possible. This technology provides a particularly attractive upgrade path for 2.16-based designs where CompactPCIe with ASI provides a unified bus structure alterna- tive to the PCI with 1 Gbit Ethernet that is provided by 2.16. The technology enablers are coming together during 2006 to enable these types of systems to be designed. One Stop Systems Escondido, CA. (760) 745-9883. [www.onestopsystems.com]. Figure 3 System configurations for CompactPCIe with ASI. a) Basic configuration, b) Dual star topology providing fault tolerance through redundancy and dynamic re-mapping. Figure 1 Host interface board, cable, switch and CompactPCIe board for interfacing to PCIe/ASI over cable.
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April 2006 37 P CI Express has the most momentum among today’s high-speed point-to- point serial links, and its adaptation for the rigorous environmental require- ments of embedded applications has cre- ated a capable foundation that will last well into the future. With the CompactPCI Ex- press standard as a foundation, applications traditionally reserved for 6U boards and systems can now be realized in the more compact and robust 3U form-factor. And even more robust solutions are possible by integrating the Intelligent Platform Man- agement Interface (IPMI) technology of the enterprise server world, with its remote diagnostic and maintenance functions, cre- ating a platform that’s suitable for the most mission-critical embedded applications. PCI Express simplifies the transition to a new generation of interconnects by adopting the same software model as PCI, making a changeover from old to new hard- ware essentially transparent to an operat- ing system. CompactPCI Express extends this major benefit by allowing existing CompactPCI boards and new CompactPCI Express boards to reside in the same back- plane, mixing old and new within the same system, as appropriate to the application. The transition from shared multidrop parallel buses such as PCI to point-to-point serial links such as PCI Express has major performance and architectural ramifications. Although 14-year-old PCI (and 10-year-old CompactPCI) are growing somewhat long in the tooth, they still provide adequate bandwidth for many embedded applications. Nevertheless, traditional buses fall far short IndustryInsight CompactPCI Express Links the Past and Future 3U CompactPCI Express combines 6U-like performance with backward CompactPCI compatibility and, when coupled with the advanced diagnostic features of IPMI, it provides an extremely robust, high-performance platform. by Paul Gaudreau Inova Computers CompactPCI and Switched Fabrics Get Connected with companies mentioned in this article. www.rtcmagazine.com/getconnected Get Connected with companies mentioned in this article. www.rtcmagazine.com/getconnected End of Article oration our goal directly ge, the ource. logy, products ies providing solutions now n into products, technologies and companies. Whether your goal is to research the latest ion Engineer, or jump to a company's technical page, the goal of Get Connected is to put you you require for whatever type of technology, nd products you are searching for. PSU #1 Translation Legacy Legacy Hybrid 3 Hybrid 2 Hybrid 1 System IN Misc. OUT Translation Board Slot 32-bit (33 MHz) CompactPCI 32-bit (33 MHz) CompactPCI 32-bit (33 MHz) CompactPCI 32-bit (33 MHz) CompactPCI 32-bit (33 MHz) CompactPCI Power Rear I/O Rear I/O Rear I/O Rear I/O X1 PCIe X1 PCIe X1 PCIe X1 PCIe CompactPCI Express CompactPCI Express CompactPCI Express CompactPCI Express CompactPCI Express CompactPCI Express Figure 1 In this example backplane, the system CPU has four direct x1 CompactPCI Express links to three peripheral boards and one translation board. The translation board provides the interface between CompactPCI and CompactPCI Express.
IndustryInsight 38 April 2006 for various types of systems with very heavy- duty I/O handling requirements and they can quickly bog down. Systems collecting large quantities of sensor data in geophysical, med- ical and military applications are typical ex- amples. Here, the more flexible and extensible point-to-point links run rings around buses. A conventional 32-bit, 33 MHz PCI bus has a maximum data transfer rate of 132 Mbytes/s. Doubling the frequency to 66 MHz boosts that figure to 264 Mbytes/s or about 1/4 Gbyte/s, a capability that both 3U (100 x 160 mm) and 6U (233.35 x 160 mm) CompactPCI boards can support. With their additional connector space, 6U CompactPCI boards can also double the data path width to 64 bits to achieve 264 Mbytes/s, and if they double both data rate and bus width, they reach a rate of 528 Mbytes/s or about 1/2 Gbyte/s. The multiplication of lines in a 64-bit implementation and the additional real estate of the 6U format, of course, add substantially to board, backplane and system cost. PCI Express, in contrast, began life beyond the GHz frontier at 2.5 GHz, and 5 GHz is now on the horizon. At 2.5 GHz, the minimal PCI Express configuration—a x1 (“by one”) link consisting of a single “lane”—supports an equivalent data trans- fer rate of 312.5 Mbytes/s unidirectionally, 625 Mbytes/s bidirectionally—almost 2/3 Gbyte/s for an entry-level implementation. (A PCI Express lane contains two sets of differential pair wiring: one set for input and one set for output.) A x4 configuration boosts those fig- ures to 625 Mbytes/s unidirectional and 1.25 Gbytes/s bidirectional, with larger lane counts bringing higher rates still— out to a maximum of 5 and 10 Gbytes/s, respectively, unidirectional and bidirec- tional, for a x32 implementation at the initial PCI Express frequency of 2.5 GHz. When considering performance in terms of bandwidth/line, the point-to-point edge over buses becomes quite dramatic. Architectural Ramifications The transition from buses to point-to- point links also has architectural ramifica- tions, which themselves affect the perfor- mance picture. A bus is a shared resource that only one device can make use of at a time. In a switched fabric made up of indi- vidual point-to-point links, many of these links can be operating simultaneously, cre- ating an additive bandwidth effect. If, for example, four x4 links in a switched fabric are all active at the same time, that adds up to 2.5 and 5 Gbyte/s (unidirectional/bidi- rectional) in aggregate bandwidth. Fabrics based on switches and point- to-point links are also far more extensi- ble than buses, supporting an essentially unlimited number of devices. PCI buses typically support only four boards at max- imum, and CompactPCI extends that to just eight. Granted, a PCI-based bus can accommodate larger numbers of boards by combining multiple bus “segments” through the use of bridges, but this can quickly become overly complex and un- wieldy, not to mention heavy in latency. In fairness, it must be mentioned that fabrics also create their own complexities and la- tencies with issues such as packet routing, dealing with out-of-order packets, etc. In the performance realm, it’s worth noting that the PCI-X follow-on to PCI dou- bled operating frequency to 133 MHz, thus passing beyond the Gbyte/second frontier, and PCI-X 2.0 added source-synchronous modes of operation that pushed bandwidth beyond 4 Gbytes/s. Nonetheless, PCI-X is extremely limited in extensibility and is typically only useful for interconnecting just two devices. In light of the high and extensible band- width provided by wedding PCI Express to the CompactPCI foundation, CompactPCI Express marginalizes the 6U performance advantage over the 3U Eurocard and greatly expands the performance range possible in the 3U form-factor (Figure 1). The smaller 3U form-factor not only has the edge in compactness and cost over 6U, but it also provides a more rugged platform due to its smaller size and lower weight. While it may be theoretically possible to design a 6U system with the same level of mechani- cal robustness, shock tolerance and vibra- tion resistance as a 3U system, this would require a considerable amount of engineer- ing, as well as substantial expense. Borrowing from the Enterprise The inherent robustness of 3U CompactPCI hardware has been well proven under the most strenuous real-world condi- tions, and CompactPCI Express has expanded the application range for that hardware with its performance and architectural boost. By adapting techniques developed for enterprise- class servers, embedded servers can achieve the same level of robustness at the system level, dramatically enhancing reliability. The Intelligent Platform Management Interface (IPMI), championed by Intel, LAN IPMI Messages Serial 802xRS232 SM-BUS 0 RS232 NV-RAM Baseboard IPMI = Intelligent Platform Management Interface IPMI (PC) Chassis PCI SM-BUS SDR, SEL, FRU FRU Seeprom 82582EM ICHS (ASPC) Baseboard
Better than ever and ready for action, LynxOS-178 once again raises the bar on standards- based development. LynxOS-178—the only DO-178B certifiable, completely POSIX- compliant RTOS – now fully meets the latest ARINC-653 requirements. The best gets even better When it comes to mission-critical appli- cations, they say you’re only as safe as your embedded operating system. We at LynuxWorks® agree wholeheartedly. That’s why LynxOS-178® is the only POSIX®-compliant RTOS that provides developers with spatial and temporal partitioning in accordance with the ARINC-653 standard. Now you’ve got even more reasons to use LynxOS-178 for all of your mission-critical applications. Further extending the value that LynxOS-178 brings to embedded systems develop- ment, ARINC-653, along with DO-178B, delivers significant software life cycle benefits to the avionics industry. Visit us on the web at www.lynuxworks.com or call us at 1-800-255-5969
Hewlett-Packard, NEC and Dell, is a well established open software standard devoted to reducing the total cost of ownership (TCO) of large IT infrastructures by optimizing diagnostics and maintenance procedures. It provides the wherewithal to deliver the reli- ability, availability, serviceabil- ity (RAS) trio of capabilities to enterprise systems for which downtime is too disruptive and expensive to be acceptable. Clearly time is money in high-end commercial appli- cations, but RAS is certainly also extremely important in mission-critical embedded ap- plications in industrial control, military, medical, transporta- tion and other computing en- vironments. Where downtime has enormous repercussions, IPMI features such as pre- boot diagnostics and operating system self- repair will be most welcome, not just in new CompactPCI Express systems, but in tradi- tional CompactPCI systems as well. The heart of the IPMI infrastruc- ture is the so-called baseboard manage- ment controller (BMC), an autonomous microcontroller to which the CPU and ma- jor on-board components are connected via a system management bus (SM-bus) (Figure 2). Based on a straight- forward request/response pro- tocol, communications over this bus are conducted using a set of standardized messages between the BMC and various compo- nents. The Intelligent Platform Management Bus (IPMB), in turn, connects the BMC to a central system resource called the satellite management con- troller (SMC). When connected to an external server running a remote management console, the BMC communicates using either an IPMI-capable Ether- net controller or a standard RS- 232 serial line. Among other aspects, IPMI supports the concept of sensor data records (SDRs) and event logs, dynamically logging such parameters as voltage, current and tem- perature and maintaining the information in nonvolatile memory. This enables proactive identification of potential hardware problems, allowing preventive adjustments to be made to operating parameters when possible. IndustryInsight 40 April 2006 Figure 3 The CompactPCI Express specification defines CompactPCI-only slots, CompactPCI Express-only slots and hybrid slots able to accommodate either type of board. In this backplane photo, the small connectors at the top of the four slots on the right are for rear I/O, and the gray connector (lower right) is a dedicated power plug for the system CPU.
Gilding the Lily Although IPMI does not require that changes be made to a system’s BIOS, do- ing so can significantly enhance the remote management of a system and its auto-recov- ery capabilities. An IPMI-aware BIOS, for example, is capable of sending alert mes- sages during the boot process to inform the remote management console about any mal- functions, which can be rectified before the system actually gets to work. It is also possible to send IPMI messages from the remote management console to the BIOS to remotely control the boot process or to change BIOS settings. Application code can also be remotely updated without operat- ing system involvement. The common system malfunction scenario of a hard disk image crash can be easily recovered remotely, for example, by commanding the IPMI-compli- ant BIOS to boot a recovery image from a me- dium such as a CD or a link such as RS-232, a local-area network connection or USB. The aforementioned IPMI capabili- ties can be further enhanced by integrating a bootable operating system kernel such as μLinux into the flash BIOS of a CPU board. Such a kernel can be utilized to ex- pand remote diagnostic and maintenance capabilities by incorporating, for example, comprehensive test functions, rich network functionality (including access to Windows- and UNIX- based servers) and support for various file systems in order to handle disk drive image repairs and updates. Moreover, for some applications, a Times μLinux kernel could also be used as the main operating system, providing all of the neces- sary driver modules for supporting onboard system components. A built-in kernel provides the ultimate in rapid system booting, and it reduces TCO by doing away with costly op- erating system licenses. Further, integrating the operating system into robust, non-wearing and vibration-resistant flash memory immu- nizes the system against the effects associated with conventional rotating-disk mass storage devices in extreme environmental conditions such as high humidity and/or temperature, or under severe shock and vibration conditions. By defining a backplane environment where CompactPCI and CompactPCI Ex- press boards coexist, the PICMG EXP.0 R1.0 standard simplifies the integration of the old and the new through a flexible backplane concept, while easing the transition between buses and point-to-point links. With this scheme, relatively undemanding functions will continue to make use of the CompactPCI bus, with boards residing in CompactPCI Express “legacy” slots, which accommodate only CompactPCI boards (Figure 3). If and whenever a bandwidth boost is required, on the other hand, a CompactPCI board in a “hybrid” slot can be swapped out for an updated, CompactPCI Express ver- sion, with no backplane or software changes required. The hybrid slot defined in PICMG EXP.0 R1.0 contains both CompactPCI and CompactPCI Express connectors. All in all, the adoption of PCI Express and IPMI will create a new class of embedded servers in the 3U form-factor, as powerful as they are rugged and compact, and as reliable as the state of the art in server management tech- nology can (at this point in time) achieve. Inova Computers North Kingston, RI. (401) 667-7218. [www.inova-computers.com]. Liquid Cooled 100W/Slot 1 ATR9 Top load 1ATR short9 Brazed construction9 Liquid cooled card cage side walls9 Accepts conduction cooled cards9 Cools up to 100W/slot power dissipation9 8 Slot VITA 41 VXS or VME64x9 Backplane with custom I/O9 MIL-STD-704 800 Watt power supply9 MIL-STD-461 EMI Hybricon Corporation 12 Willow Road Ayer, MA 01432 ISO 9001-2000 Certified Call Today 1-877-HYBRICON www.hybricon.com Extreme environments require extreme solutions... The Challenge - Develop the next evolution of ATR cooling.. Mission Complete! Hybricon Corporation is a true solutions company providing integrated system solutions, electronic enclosures, and backplanes for high performance military and ruggedized COTS applications. Hybricon has a successful track record of proven and deployed COTS solutions that have been designed to meet stringent military requirements. IndustryInsight April 2006 41
April 2006 43 M atching the solution to the applica- tion is key to developing designs that are both affordable and scal- able for future performance upgrades, and benefit platform longevity. The requirements of applications for which embedded systems are being designed widely vary in complex- ity, cost and performance. These present extreme challenges for designers of systems that must support not only a wide range of applications, but a continuously changing set of performance requirements. Whether it’s ever increasing bandwidth needs or chang- ing communications standards, protocol- based interconnects and switch fabrics offer unique benefits to addressing these issues. CompactPCI has a rich history in embedded design; a logical step to extending its capa- bilities is adding a switch fabric architecture to your current product line. Using the same interconnect across your entire design can leverage your knowledge of the protocol and its interfaces. In fact, there are numerous benefits to choosing a single system-wide interconnect. These include con- trolling development costs, design simplifica- tion, quick debug and system verification. Scaling to Switched Fabrics Many applications require complex switched fabric architectures, but let’s start by looking at scalability and where it starts, as a simple interconnect. When choosing an interconnect between two devices it is im- portant to consider that the interface must not only meet your current requirements, but is also extendable to match your future needs. An interconnect that can also be used throughout your system at multiple band- widths and cost points is also important. RapidIO technology was designed specifically as a widely applicable, flexible, extensible system interconnect for embed- ded infrastructure equipment including networking, storage and communication systems. RapidIO can be used as a simple chip-to-chip interconnect, using 8- or 16- bit parallel interfaces, or 1x to 4x serial interfaces at speeds ranging from 1.25 Gbits/s to 3.25 Gbits/s per link. Future in- terfaces are planned for speed including 5/6.25 Gbits/s per link (Table 1). Parallel RapidIO will provide an ex- tremely low latency connection that has high bandwidth and is suited for onboard processor interconnection. Serial RapidIO has the advantage of low pin count along with multiple width and speed options, which can be matched with the bandwidth requirements of each link. IndustryInsight System Scalability with Switched Fabrics in CompactPCI The benefits of a switched fabric architecture in CompactPCI begin with the use of a serial interconnect as a simple device-to-device interface extending to a fully redundant high-availability system-wide fabric. by Tom Cox RapidIO Trade Association CompactPCI and Switched Fabrics Get Connected with companies mentioned in this article. Get Connected with companies mentioned in this article. www.rtcmagazine.com/getconnected End of Article oration ur goal directly ge, the urce. logy, products ies providing solutions now n into products, technologies and companies. Whether your goal is to research the latest ion Engineer, or jump to a company's technical page, the goal of Get Connected is to put you ou require for whatever type of technology, nd products you are searching for. Parallel RapidIO Clock Rate 8-bit Mode 16-bit Mode PEAK Sustained 32 byte Op Sustained 256 byte Op PEAK Sustained 32 byte Op Sustained 256 byte Op 250 MHz 8 Gb/s 4 Gb/s 7.5 Gb/s 16 Gb/s 8 Gb/s 15 Gb/s 500 MHz 16 Gb/s 8 Gb/s 15 Gb/s 32 Gb/s 16 Gb/s 30 Gb/s 750 MHz 24 Gb/s 12 Gb/s 22.5 Gb/s 48 Gb/s 24 Gb/s 45 Gb/s 1 GHz 32 Gb/s 16 Gb/s 30 Gb/s 64 Gb/s 32 Gb/s 60 Gb/s Serial RapidIO Clock Rate 1-bit Wide 4-bit Wide PEAK Sustained 32 byte Op Sustained 256 byte Op PEAK Sustained 32 byte Op Sustained 256 byte Op 1.25 GHz 2 Gb 1 Gb 1.8 Gb 8 Gb 4 Gb 7.2 Gb 2.5 GHz 4 Gb 2 Gb 3.6 Gb 16 Gb 8 Gb 14.4 Gb 3.125 GHz 5 Gb 2.5 Gb 4.5 Gb 20 Gb 10 Gb 18 Gb Table 1 RapidIO offers a broad range of interface speeds and widths.
IndustryInsight 44 April 2006 In both cases, whether choosing paral- lel or serial RapidIO, only the physical layer of the protocol is changed. All the other as- pects of the interconnection stay the same requiring no software changes to the system. The fact that multiple speeds and widths can work together seamlessly in a system positions RapidIO well for a flexibility that enables upgrades and system longevity. The RapidIO protocol can be transmit- ted over anything from serial to parallel in- terfaces, from copper to fiber media. This en- ables further flexibility to develop innovative solutions to a broad base of applications. The use of RapidIO as a point-to-point interconnect does not require the implemen- tation of the device-addressing portion of the protocol. The transport layer specifica- tion of RapidIO defines the device address- ing models for the technology. The transport specification is independent of any RapidIO physical or logical layer specifications. When developing more complex systems where thousands of devices are in a system, the transport layer is key to flexibility and redundancy in the system (Figure 1). RapidIO can support virtually any system topology. The device IDs do not convey any intrinsic information about where they are located in the system. It is the responsibility of the interconnection fabric to discover where the devices are located and to forward packets to them based on target device ID only. The Rapi- dIO network learns during the system dis- covery phase to bring up where devices are located. Switches are programmed to understand the direction, although not the exact location of all devices. When device locations change, as might occur during hot swap or failover situations, only the switches need to be reconfigured to un- derstand the new system topology. These advantages of RapidIO fabrics provide virtually unlimited flexibility, scalability and many ways to design redundancy into your system. CompactPCI Serial RapidIO The CompactPCI Serial RapidIO (PICMG 2.18) specification adds serial RapidIO as an alternative board-to-board interface for the standard CompactPCI platform. This provides a significant im- provement in bandwidth compared with Host Card RapidIO Fabric CPU CPU CPU MEM MEM MEM Ethernet MEM RapidIO ASIC Physical Layer Interface NPU Line Card DSP Control & Data CPU Traffic Aggregation DSP DSP DSP DSP DSP DSP DSP DSP DSP Ethernet/IP ATM/SONET Infiniband/Fibrechannel TDM Voice Traffic Figure 1 Efficient use of multiple RapidIO parallel and serial links includes a system with a mixture of parallel RapidIO on the host card, Serial RapidIO 4x links for the backplane and Serial RapidIO 1x links for the DSP farm. The PowerMP concept is designed to provide off- the-shelf and off-the-chart performance for your critical computing needs in demanding environments. Each MP system is a high-performance, low-cost COTS-based multiprocessor computing solution based on industry standards and Pentium and/or PowerPC architecture. The new PowerMP6 – a multi-Pentium, ready- to-use solution When you place a premium on software productivity and performance turn to the turnkey computer system that sizzles—PowerMP6. The newest in the PowerMP line, the PowerMP6 consists of multiple Pentium-M boards in a 19-inch rack. Running Red Hat Linux on the Intel processors supports software productivity and portability through an extensive set of open source and commercial tools and libraries. Performance is dictated by the number of Pentium M processors the system runs and the PowerMP6 available in various customized configurations of up to eight processor boards in a rack. The PowerMP6 features optimized message passing interface (MPI) for multiprocessor communications and contains software tools geared for such tasks as real-time performance analysis, remote control operations and monitoring system management. The PowerMP4-60 – RapidIOTM system entry. The PowerMP4 fills the embedded industry’s need for reliability, increased bandwidth and faster bus speeds. It combines PowerPC and Pentium-M technology and takes advantage of the outstanding compute power to power dissipation ratio of the PowerPC technology as well as the wide spectrum of software tools available on PC platforms. PowerMP4-60’s RapidIOTM high-performance and packet-switched interconnect technology meet your demanding embedded system needs. The specialists in embedded performance Thales’ Computers include development of commercial and ruggedized VMEbus & CompactPCI systems solutions based on PowerPC and Pentium microprocessors. Thales’ products are optimized for a wide variety of applications in the military, aerospace, transportation, communications, and industrial markets and are used by blue chip customers worldwide. www.thalescomputers.com Nothing empowers performance like PowerMP! For more information please contact: Luc Torres Tel: 33(0)4 98 16 33 95 e-mail: luc.torres@thalescomputers.fr THA068_187x121_RTC US_GB 21/
IndustryInsight April 2006 45 traditional CompactPCI interfaces: PCI, H.110 and Ethernet. These traditional inter- faces are not required, but are also not pre- cluded. So, a heterogeneous CompactPCI system, supporting both new high band- width as well as legacy, can be easily con- structed. The PICMG 2.18 standard chose to use the existing 2 mm CompactPCI con- nector. This both ensures a level of mechan- ical compatibility and keeps the connector costs reasonable. After performing careful signal integrity simulations, it was deter- mined that 1.25 Gbits/s was the maximum reliable speed for a serial RapidIO differ- ential pair on this platform. Each board can have up to four bidirectional 4x serial RapidIO links running at 1.25 Gbits/s for a total of 40 Gbits/s of aggregate bandwidth between the board and backplane. For Serial RapidIO technology, two transmitter specifications allow for solu- tions ranging from simple board-to-board interconnect to driving through two sepa- rate connectors and across a backplane. Two transmitter specifications were desig- nated: a short-run transmitter and a long- run transmitter. The short-run transmitter is used mainly for chip-to-chip connections either on the same printed circuit board or across a single connector such as that for a mezzanine card. The minimum swings of the short-run specification reduce the over- all power used by the transceivers. A user can further reduce the power by lowering the termination voltages. The long-run transmitter uses larger voltage swings that are capable of driving across backplanes. This allows a user to drive signals across two connectors and common printed circuit board material. To ensure interoperability between drivers and receivers of different vendors and technologies, AC coupling must be used at the receiver input. RapidIO technology has become the de facto interconnect and fabric standard for embedded systems being deployed to- day, providing increased performance, im- proved efficiency and lower cost. RapidIO technology is supported by a broad ecosys- tem of leading vendors with multiple ven- dors shipping production switches, DSPs, processors, end-points, FPGAs, boards, software and systems. Serial RapidIO tech- nology offers a higher-speed physical layer that can be configured to match bandwidth requirements with different speed variants and numbers of lanes. It builds on the com- munication industry’s common roadmap at the Serial physical layer, using a variant of IEEE 802.3 XAUI today for 3.215 Gbits/s and a variant of the OIF CEI work on 5 and 6 Gbits/s in the future. The RapidIO fabric provides a robust packet-switched system-level intercon- nect. RapidIO can be used to develop de- signs that are both affordable and scalable for future performance upgrades. The RapidIO technology provides a partitioned architecture that can be enhanced in the future. It enables higher levels of system performance while maintaining or re- ducing implementation costs. A RapidIO end-point can be implemented in a small silicon footprint. Proven industry-stan- dard signaling schemes (LVDS, XAUI) are used for the physical interfaces. Error management includes the ability to detect multi-bit errors and survive most multi- bit and all single bit errors. Even with all these capabilities, the RapidIO protocol overhead and latency are comparable to current bus technologies and significantly better than local area network-based fab- ric technologies such as Ethernet. RapidIO Trade Association [www.RapidIO.org]. 1 2 3 4760 Richmond Rd / Cleveland, OH 44128 Tel: 216.245.4180 / Fax: 216.292.0561 www.embeddedplanet.com Are You Board With Me? design. The next generation of connected devices. develop. Your products based on our platform. deploy. Your solution faster. Start with an AMCC PowerPC 405 Processor. Specify your I/O requirements. Choose your operating system. Relax while Embedded Planet delivers your rugged and reliable system. design. develop. deploy. d 2 d 1 d 3 EP885 Stack Advert V4.indd 1 1/11/2006 1:24:11 PM
1.800.443.2667 • sales@dtims.com • http://www.dtims.com/rtc CPU Boards - Switch Blades - Rackmount Systems - Modular Platforms Computer Modules - System Integration - Custom Designs - Outsourcing Capabilities Three Decades of Embedded Solutions All trademarks and tradenames are the property of their respective owners. AdvancedTCA Nodes and Switches > Find out more at www.dtims.com/rtc • DTI Board and System Level Products - AdvancedTCA - CompactPCI - COM Express and ETX - PCI/ISA and Embedded PCI-X - Custom Offerings • DTI Technical Presentations will be offered hourly at GLOBALCOMM - Booth 17051 - AdvancedTCA Gotchas - AdvancedTCA Fabrics - COM Express Overview • Engineering and Manufacturing are under-one-roof, leading to a reduced time-to-market. B U I L D I N G P L A T F O R M S O L U T I O N S AdvancedTCA • CompactPCI • PCI/ISA • Embedded PCI-X • ETX • COM Express • Custom Design and Manufacturing
April 2006 47 Executive Interview RTC: Over the years that we’ve been following Diversified Technology, the company has certainly lived up to its name, offering a variety of embedded computer solutions from full custom through industry standard and semi- standard and boards and systems. First off, how do you balance your custom and standard activity within the same workplace? Secondly, at what point does a semi-standard or semi-custom design become a full custom design. Busby: Initially, allow me to thank RTC magazine for the opportunity to address your readers. You are certainly correct that Diversified Technology, Inc. (DTI) has lived up to its name over the last thirty-five years. As far as balancing custom and stan- dard activity within the same workplace, it comes down to one thing—great people. We pride ourselves on the longevity of the company and its employees. Longev- ity has created an experienced software, hardware, systems and manufacturing staff that has seen numerous projects. They enjoy developing catalog products as well as digging deep with customers to solve a specific problem with them. Solv- ing problems is always a satisfying expe- rience for DTI and its employees. In addition, we are involved in the Communications, Government / Mili- tary and Commercial markets, giving DTI employees the ability to apply what is learned in one market and introduce it into another market. For example, we took a communication platform provided to a major TEM and ruggedized it for a shipboard communication platform. Af- ter all, a ship is a small city with similar bandwidth needs to a telecommunications installation. The line between semi-standard or semi-custom or a full custom design is more difficult. We have always been re- sponsive to customers’ needs (they pay the bills you know), so non-standard de- signs are something we see very often and are comfortable with. For our ISO 9001 system, we consider it a full custom de- sign when we put it under revision control for the customer. RTC: ATCA has been the great hope of a number of standards-based board makers for the past several years, yet, to date, it has failed to generate the expected sales and revenue. When do you believe ATCA will round the bend and become a mainstream technology for the merchant-market embedded computer industry? What indicators are out there that this transition is hap- pening? Busby: ATCA is an architecture DTI has been involved with from the standards definition through initial interoperability workshops to DTI’s early single proces- sor node boards (processor boards) and unmanaged hub boards (switches). DTI now offers dual processor node boards, fully managed hub boards and full ATCA systems. I am unsure what qualifies Get Connected with companies mentioned in this artic www.rtcmagazine.com/getconnected Get Connected with companies mentioned in this article. www.rtcmagazine.com/getconnected Get Connected with companies and products featured in this section. www.rtcmagazine.com/getconnected Ad Index End of ArticleProducts Get Connected with technology and companies providing solutions now Get Connected is a new resource for further exploration into products, technologies and companies. Whether your goal is to research the latest datasheet from a company, speak directly with an Application Engineer, or jump to a company's technical page, the goal of Get Connected is to put you in touch with the right resource. Whichever level of service you require for whatever type of technology, Get Connected will help you connect with the companies and products you are searching for. www.rtcmagazine.com/getconnected Get Connected with technology and companies providing solutions now Get Connected is a new resource for further exploration into products, technologies and companies. Whether your goal is to research the la datasheet from a company, speak directly with an Application Engineer, or jump to a company's technical page, the goal of Get Connected i in touch with the right resource. Whichever level of service you require for whatever type of technology, Get Connected will help you connect with the companies and products you are searching for. www.rtcmagazine.com/getconnected RTC Interviews Pat Busby, CEO of Diversified Technology
48 April 2006 ExecutiveInterview ATCA as a mainstream technology for the merchant-market embedded computer industry, but for DTI, ATCA is already a mainstream product. Our indicators are design wins for processor boards, switches and our TARGA-5 and TARGA-14 sys- tems. These systems provide blade servers with maximum performance, non-block- ing wire speed switches and NEBS-ready chassis, allowing service providers the flexibility to deploy new revenue generat- ing services in an evolving marketplace. Our worldwide ATCA shipments have increased significantly in 2006 over 2005 levels. Given the cost advantages associ- ated with ATCA compared to big board custom systems, we expect to see the ATCA market continue to grow. Our cus- tomers tell us that the cost advantages of a standards-based board coupled with DTI’s capabilities to provide product differentia- tion provide significant advantages over the cost of full custom board development. RTC: Diversified is one of the few com- panies that has developed ATCA for applications outside of the communica- tions business. Can you share with our readers some of the application areas that can take advantage of the larger form-factor and high performance of the standard boards? What are the characteristics that are most in demand that steer customers toward ATCA? Busby: Our primary areas of ATCA devel- opment outside the communications business would be InfiniBand (PICMG 3.2 Standard). The InfiniBand-based TARGA systems al- low 10 Gigabit throughput at a lower latency than in current systems. In addition, it is our belief that a move to 20 Gigabit and higher throughputs will maintain InfiniBand’s throughput lead over other fabrics. The larger form-factor works well from front-end security systems to storage platforms to voice, data and video traffic management systems. The characteristics that steer customers toward ATCA are stan- dards-based ATCA platforms, allowing the customers to concentrate on their software needs and leave their hardware needs to us. RTC: Diversified has also been a staunch supporter of CompactPCI and PICMG 2.16, which we have been lumping to- gether from a market standpoint. Some industry reports have put the volume of business in the cPCI/2.16 market as high as $1.2 billion, split almost evenly between merchant market and captive suppliers. Do you believe this number is valid? Is much of this business from communications customers who need to upgrade but are timid about jumping into ATCA with both feet? Busby: CompactPCI and PIGMG 2.16 (as well as PCI) have all been good to DTI. For us, the low-power Intel Pentium M and Pentium 4 processors with reduced ther- mals and increased functionality have been a real boost for CompactPCI and ETX modules by providing performance under constricted space requirements. We would not argue with the industry reports you reference. I would also agree that much of this business is from customers who need to upgrade, but I do not see it as them be- ing timid about jumping into ATCA. In spite of the lower costs with standards- based ATCA products, there is still a cost increase over CompactPCI and this, along with space requirements, appears to be sustaining CompactPCI. Many Government / Military custom- ers also appreciate that DTI is one of a very few U.S. companies capable of going from concept to design to manufacture of a board or system, all in-house, something very unique in our industry. RTC: MicroTCA has been heralded in many areas as the next hope for the mer- chant market for boards and systems. Yet, the specification is not yet formalized, there are factions looking for a more rug- ged implementation, and there may be a defection of some of the players. Do you see MicroTCA in its present form as a vi- able form-factor? What application areas do you think it will play strongest in. Busby: MicroTCA in its present form is a viable form-factor, but as you point out, there is still a substantial risk to going too far—too fast—when specifications are in flux. Technically, MicroTCA is substan- tially different from ATCA, so it’s not sim- ply a smaller version of ATCA. It is unclear to me if the differences in management and other areas in MicroTCA are clearly un- derstood throughout the industry. With all new form-factors and standards there is a risk that it will not be universally adopted. At DTI, we felt that ATCA had reached its “time” and took the gamble early on. If MicroTCA is accepted as a vi- able competitor, we would expect the pri- mary application areas to be traditional CompactPCI, VME and I/O-centric ap- plications. Currently, we continue to watch MicroTCA specification development in anticipation of a timely market entry. RTC: There has been significant specu- lation that the European Union’s direc- tive on the Restriction of Hazardous Substances (RoHS) will cause problems as many leaded components go to end of life. One of the technology areas that may well be under fire is PCI. As Intel and
April 2006 49 ExecutiveInterview these reasons. Solder joint evaluations on Pb- free components that could also be used in a leaded board assembly process are ongoing and may provide a significant opportunity to extend leaded boards where needed. DTI’s strategy is to have both RoHS and non-RoHS-compliant production lines for as long as the market demands such products. In DTI’s case we have already made substantial capital expenditures to provide Pb-free board assembly processes where needed. RTC: The potential acquisition of Bell- South by AT&T (née SBC) is likely to stir the pot in the communications busi- ness, putting direct competitor Verizon and most of the cable companies on no- tice that the 400 lb ($200 billion) gorilla is in town. There is speculation that such mega mergers will impact the merchant- market, standards-based embedded com- puter market. Some believe the increased competition and need for quick time-to- market will favor the application of such boards and systems. On the other hand, others speculate that the consolidation of infrastructure will eliminate the need for new capital expenditure and thus put a wet blanket on the industry. What im- pact, if any, do you believe such mega- mergers will have on the embedded com- puter business? Will the convergence of wired and wireline, voice data and video into a single network be a boon to inde- pendent board and system makers? Busby: We believe the mega-mergers will be positive for the embedded computer business, when coupled with Moore’s Law. Regardless of the mega-mergers, we expect to see perfor- mance enhancements in the industry to drive the industry to upgrades that make sense. A real-life example of this is a TEM that DTI has taken from 133 MHz to 200 MHz to 500 MHz to 900 MHz to 3.2 GHz dual Xeon processors. Capital expenditures will con- tinue to make sense with such performance increases, regardless of the mega-mergers. Convergence or “quad play” or “bundles” if you will, of home phone, Internet, Video (IPTV or cable) and in some cases wireless, will continue to push phone and cable rivals to deliver more competitive packages, driv- ing the need for more systems. Differentiated features (not the approx- imate 15% equipment costs) are their path to maintaining or increasing revenues. The lower costs achievable through stan- dard-based independent board and system makers like DTI should be a large part of the cost cutting desired in this competi- tive environment. RTC: Wi-Fi has also captivated much of the general press recently and it’s been postulated that it may yet be a contender to Verizon’s Fiber-To-The Home (FTTH) or AT&T’s fiber to the community with copper tentacles, or some cable configuration from the likes of Comcast, Time Warner, Cox or others. What, if any, impact will this technology have on the embed- ded-computer business? It’s also been speculated that Wi-Fi or some similar approach will have a broader applica- CompactPCI ShowcaseFeaturing the latest in CompactPCI technology Twin Industries Part # 2000-6U-EXTM 6U cPCI Extender Card Test Points for all Signals Power and Ground Planes Fuses for all Voltages Quickturn Customization Available Twin Industries Phone: (408) 358-2505 Fax: (408) 358-2506 E-mail: sales@twinind.com Web: www.twinind.com T2-6U-cPCI Octal ADSP-TS201 TigerSHARC 6U cPCI Board Eight ADSP-TS201 TigerSHARC® DSPs providing 28.8 GFLOPS and 115 BOPS of processing Two FPGAs - I/O interfacing, routing, and coprocessing ATLANTiS architecture - over 10 GB/sec of external I/O throughput via FPGA 64-bit 66 MHz PCI interface via BittWare’s SharcFIN PCI-DSP bridge Two PMC sites with PMC+ extensions BittWare, Inc. Phone: (603) 226-0404 Fax: (603) 226-6667 E-mail: info@bittware.com Web: www.bittware.com CPB4612 - PICMG 2.16 compliant CPU Board Intel® Pentium® M Processor with speeds up to 1.8GHz and 2MB L2 Cache Intel® 855GME Chipset with 400MHz Front Side Bus 128MB to 2GB ECC DDR PC-2700 SDRAM Dual 100/1000 Ethernet Interface 10/100 Ethernet Interface 64/66 PMC Site Onboard 2.5” HDD or 32/33 PMC site Diversified Technology, Inc. Phone: (800) 443-2667 Fax: (601) 856-2888 E-mail: sales@dtims.com Web: www.dtims.com rtc0604_showcasev1.indd 1 4/12/06 9:15:12 AM
50 April 2006 ExecutiveInterview tion in other areas such as industrial control, medical monitoring and other typical applications of industrial em- bedded computers. Busby: Wi-Fi has certainly captured a lot of press. More than 2,200 products have been Wi-Fi-certified as compliant based on the IEE 802.11 standard, and over 100 million Wi-Fi chipsets were shipped in 2005. Embedded Wi-Fi radios appear to be used in laptops and PDAs, but with PC card slots, PCI/ISA bus and USB radios, many options are available. Coupled with WPA (Wi-Fi Protected Access), an im- proved security standard for wireless net- works, we do expect broader application of Wi-Fi in industrial embedded computers. RTC: Diversified is a division of a large energy company, Ergon. Can you pro- vide our readers with a little back- ground into this relationship and what it means to customers and potential customers? Busby: Certainly. Ergon, Inc. (www.er- gon.com) is the parent company of DTI (www.dtims.com) and has been for over twenty-eight years. For anybody con- cerned about DTI’s viability since DTI is a young thirty-five year old company, they can take comfort in the fact that its parent company has been around for fifty-two years. Seriously, for customers, it offers a great deal of comfort that one of the larg- est privately held companies in the U.S. provides financial stability and long-term commitment to the embedded computer market. Longevity through industry cy- cles like the dot com bust gives customers a level of confidence that otherwise might not be there. Finally, as a result of Ergon’s involve- ment, expansion into markets such as On- Board-Vehicle-Power and the RF Solu- tions allows DTI to develop IP outside its traditional markets. RTC: Over the past years we’ve seen tremendous growth among companies producing small form-factor embed- ded computers ranging from ETX and PC/104 to 3U cPCI and COMM Ex- press. Applications range from mili- tary and aerospace to industrial con- trol and medical diagnostics/therapy. Is Diversified looking to enter the small form-factor, embedded-computer busi- ness in the near future? What are the advantages? Disadvantages? Busby: In addition to custom boards, DTI has delivered multiple ETX (small form-factor) boards and systems for years and will release its first dual core COMM Express board in 2006. Beyond the obvious advantages of smaller enclo- sures, DTI’s focus on ETX has been on low power and in many cases ruggedized configurations operating in isolated en- vironments with operating temperatures ranging from -40° to +75ºC. The disad- vantages are the lack of raw processing power and peripheral devices. In providing the hardware solution needed to solve a specific problem through DTI’s custom capabilities (outlined by nu- merous case studies on DTI’s Web site), or a software solution such as a custom SNMP (Simple Network Management Protocol) agent, we encourage customers to think solution first and form-factor sec- ond. Thanks, again. DIVERSIFIED TECHNOLOGY www.rtecc.com See at the RTECC Boston Sheraton Framingham Hotel Visit Diversified Technology at the Real-Time & Embedded Computing Conference (RTECC). Learn why we believe that cPCI or PICMG 1.0 products might be threatened; and Solder joint evaluations on Pb-free components (that could also be used in a leaded board assembly process) are ongoing and may provide a significant opportunity to extend leaded boards where needed. Hear about our strategy to have both RoHS and non-RoHS-compliant production lines for as long as the market demands. Go to www.rtecc.com/boston and pre-register for this complimentary event. See you on Thursday, April 27th when we’ll be talking about providing Pb-free board assembly processes and much, much more. April 27, 2006 rtecc_diversified_april.indd 1 4/11/06 11:11:23 AM
By functionally disaggregating commercial computing resources and housing them in a standardized footprint, purpose-built enclosure, Slice provides resilience with superior thermal and kinetic management. This open and modular design allows for spiral technology refresh, extending computing infrastructure investments for complete lifecycle management. Themis’ real-time resource manager integrates all computing resources, under dynamic policy control, to optimize application quality of service. Themis Slice is transformational technology offering the most robust and efficient platform available. No other platform will enable the 21st century war fighter as effectively. www.themis.com (510) 252-0870 © 2005. Themis Computer, Themis, Themis logo and Themis Slice are trademarks or registered trademarks of Themis Computer. All other trademarks are property of their respective owners. Cool. Calm. Collected. Transformational. Cool. Innovative and cost-effective cooling system can tame the hottest of processors in four 100 Watt sockets that support eight processor cores. Air and liquid heat exchanger options. Calm. Standardized mechanical footprint designed to survive in high shock and vibration environments - up to 40G shock and 1 grms vibration. The Themis Slice™ architecture can handle whatever you or the outside world throw at it. Collected. Scalable - up to 16 processor cores. High-density, processor-independent architecture implemented with SPARC®, IBM®, PowerPC and x86 technology. Solaris™, Windows®, and Linux® operating systems. All networked in a single system. All managed in real-time. Themis’ Slice technology is a breakthrough in lifecycle management for mission-critical computing.
April 2006 53 Software&Development Tools Real-Time Java Achieving RAMS Objectives in Hard Real-Time Java Software RAMS—Reliability, Availability, Maintainability and Safety—represents software quality objectives that are relevant to most embedded systems development. Disciplined use of real-time Java technologies can help developers achieve RAMS objectives. by Kelvin Nilsen Aonix C reating reliable software is largely a matter of applying careful and disciplined software development and main- tenance practices. However, the choice of programming language also plays an important role. Two topics that are af- fected by programming language issues include simplicity and portability. Use of a simpler programming language is more likely to result in reliable software because programmers are less likely to accidentally misuse the language when they misunderstand its semantics. Programmers who are dealing with less complexity are less likely to make programming errors. C++, for example, is a very complex language, and certain of its features, such as overriding standard operators, are often misunderstood by pro- grammers. Teams that have used C++ for large development efforts generally reach the conclusion that every team member must be an expert C++ programmer, or the whole team will suf- fer the mistakes made by less experienced developers. One area in which C and C++ are much more complex than Java is the way that they manage the allocation and deallocation of temporary memory objects. C programmers use malloc() and free() function calls. C++ programmers use the new and delete() services. In both C and C++, program reliability will suffer if memory becomes fragmented, and preventing fragmen- tation is largely outside the realm of control of the application developer. Further complications with dynamic memory man- agement in C and C++ programs are the risks that the memory for allocated objects will not be reclaimed, and that program components will retain pointers to objects that have been re- Get Connected with companies mentioned in this article. www.rtcmagazine.com/getconnected Get Connected with companies mentioned in this article. www.rtcmagazine.com/getconnected Get Connected with companies and products featured in this section. www.rtcmagazine.com/getconnected Ad Index End of ArticleProducts Get Connected with technology and companies providing solutions now Get Connected is a new resource for further exploration into products, technologies and companies. Whether your goal is to research the latest datasheet from a company, speak directly with an Application Engineer, or jump to a company's technical page, the goal of Get Connected is to put you in touch with the right resource. Whichever level of service you require for whatever type of technology, Get Connected will help you connect with the companies and products you are searching for. www.rtcmagazine.com/getconnected Get Connected with technology and companies providing solutions now Get Connected is a new resource for further exploration into products, technologies and companies. Whether your goal is to research the latest datasheet from a company, speak directly with an Application Engineer, or jump to a company's technical page, the goal of Get Connected is to put you in touch with the right resource. Whichever level of service you require for whatever type of technology, Get Connected will help you connect with the companies and products you are searching for. www.rtcmagazine.com/getconnected Get Connected with companies and products featured in this section. www.rtcmagazine.com/getconnected Stack for main thread Stack for third spawned thread Stack for second spawned thread Stack for first spawned thread Main thread’s stack height at point of spawning other threads Figure 1 Organization of scratchpad memory.
Software&DevelopmentTools 54 April 2006 claimed. These common programming errors are respectively known as memory leak and dangling pointer. Memory management in traditional Java is much simpler, and thus much more reliable, than the techniques used in C and C++. Java’s automatic garbage collection system reduces mem- ory leaks by automatically reclaiming objects that are no longer in use, and garbage collection totally eliminates the possibility of dangling pointer errors. Typical Java garbage collection im- plementations also defragment memory in order to further en- hance reliability. The draft safety-critical Java profile provides the same benefits, but does so without the use of traditional trac- ing garbage collection. Instead, it allocates temporary objects on the run-time stack, and the memory for these objects is instantly reclaimed when control leaves the currently executing method. All temporary memory allocation is organized as a stack to pre- vent memory fragmentation. Additionally, special compile-time analysis of the application programs guarantees the absence of dangling pointers. Figure 1 illustrates the organization of temporary memory after a main thread has spawned three child threads, setting aside portions of its run-time stack to serve the temporary memory needs of each of the spawned thread’s run-time stacks. The safety conventions allow pointers from inner-nested objects to outer-nested objects, as illustrated with the solid-filled arrow- heads in this figure. Pointers in the other direction are disallowed. Enforcement of this protocol is performed at compile time by a special hard real-time byte-code verifier based on annotations provided in the source code. Reliability benefits from portable development methodolo- gies in two important ways. First, programmers who are able to target a portable platform are less likely to make programming errors because they misunderstand or overlook incompatibilities between platforms. Second, programming languages that support portability between different platforms make possible far greater reuse of software components that were developed for one plat- form but reused on another. When such software is reused, it can be reused exactly as is, without any changes required for port- ing. For typical deployments, this means a far greater percentage of the complete software system is comprised of mature time- proven software components. Within the domain of real-time programming, the Real-Time Specification for Java (RTSJ) does not support portable real-time semantics. Compliant implementations of this specification may differ in significant and incompatible ways, preventing real-time Java code that was developed and tested on one RTSJ implemen- tation from running correctly on another. Compliant RTSJ im- plementations may differ in the scheduling of real-time threads, the times at which task deadline and CPU cost overruns are de- tected and handled, access to scope-allocated objects within the standard libraries, and allocation of objects within scoped-mem- ory contexts by the standard libraries. The proposed safety-criti- cal Java profile addresses these portability issues by subsetting from the full set of RTSJ capabilities, and carefully specifying the required semantics of the subset to ensure that all compliant implementations represent the same portable real-time program- ming platform. Availability Availability means that high-integrity software must be al- ways ready to perform its function. Availability is often mea- sured in terms of a quantity of nines. For example, “five nines” availability means the system is running reliably 99.999% of the time. Clearly, reliability contributes to availability by extending the mean time between system failures. But high availability also means reducing the time required to recover from failures when they do occur. Providing fast, deterministic restart of a failed system is an obvious requirement for high-availability applications. Achieving this is not trivial. In typical Java environments, startup is espe- cially troublesome because the startup process includes dynamic loading and JIT compilation of byte code. The draft safety-criti- cal Java profile requires static compilation, initialization and link- ing of components. In traditional Java, the initial values of many shared variables, even of so-called constant variables, depend on the order in which certain non-deterministic startup activities are performed. The safety-critical profile’s byte-code verifier, on the other hand, enforces fully deterministic initialization of shared static variables. The safety-critical Java linker binds all of the components together and initializes shared memory in the static load image. The large majority of this load image can be burned into ROM and accessed directly out of ROM. Occasionally, highly available systems experience hardware failures. When hardware must be replaced, it may also be neces- sary to replace
April 2006 55 Software&DevelopmentTools plug-and-play devices, but the protocols for use of plug-and-play technologies are not especially reliable. Often, conflicts between device drivers supplied by different vendors result in unreliable operation of the newly configured environment. A goal for the safety-critical Java profile is to support reliable and deterministic reconfiguration of device drivers, both for situations in which the device drivers are replaced without down time, and for situations in which hardware replacement requires system reboot. Figure 2 illustrates the ability to safely and efficiently recon- figure temporary memory in order to support on-the-fly replace- ment of device drivers. Here, the three threads that had been pre- viously spawned by the main thread have been terminated and replaced with four new threads that occupy the same memory. Note that the last-in, first-out process of reclaiming memory from the three original threads has the beneficial side effect of elimi- nating all memory fragmentation within those thread scopes. As with many other issues, the safety-critical Java profile tackles this challenge using a combination of programmer an- notations, special byte-code verification and reliable run-time memory management services. This makes it possible to guaran- tee at compile time that a given device driver is a suitable replace- ment for another. Support for redundant computations and failover processing is not directly supported by the safety-critical Java profile. It is worthwhile to mention that the Java platform was originally in- troduced as an Internet programming language. As such, there is considerable experience using Java for networked applications. Since the draft safety-critical Java profile establishes a strong foundation for reuse of portable hard real-time software compo- nents, it will be straightforward to develop portable libraries to support safety-critical networked communications in support of fault-tolerant and high-availability redundant computations. Maintainability Maintaining real-time software is particularly difficult be- cause traditional interface declarations do not reflect all of the constraints required for reliable composition of the real-time components. This means developers who are called upon to make changes to existing software cannot determine by looking at the component interface alone what rules they must follow in order for their maintenance changes to integrate reliably with other ex- isting software. Maintainers of real-time software must search for all the contexts in which particular components “reside” in order to determine what sort of changes they may make to those components without compromising the reliability of the system. Compared with C and C++, Java has shown tremendous strengths as a platform to support easy maintenance and integra- tion. This is because all of the Java software is very portable, and because strong object-oriented abstractions mean that indepen- dently developed components integrate cleanly, without compro- mising the integrity of each other’s encapsulation boundaries. C, in contrast, offers very little to help manage the complexity of ever-expanding software systems. With its object-oriented fea- tures, C++ does much better than C at separating concerns of independent software development teams in order to facilitate software maintenance and scalability issues. However, the lack of true portability, the inherent complexity in the language itself,
56 April 2006 Software&DevelopmentTools and its lack of automatic garbage collection make C++ a much more difficult tool than Java in its support for software mainte- nance and scalability. The proposed safety-critical Java profile contributes to maintainability by requiring real-time interface constraints to be represented in source code using standard Java annotations, enforcing the consistency of these annotated interface require- ments with a special byte-code verifier, and providing a static analysis tool to automatically determine the memory and CPU- time requirements of particular components. Tools to automate the required consistency checking and resource needs analysis are not generally available for C and C++ development. Safety DO-178B Level-A certification requires that all code cover- age analysis and testing be performed on the native machine lan- guage, and that responsibility for every machine code instruction and for every test case be traceable from original system require- ments to architecture and design, to source code and test plans, and finally to machine code. If certain machine instructions are not exercised sufficiently by the existing test cases, developers are required to analyze whether the code is really necessary to satisfy the system requirements. If that code is not necessary, the corresponding source code should be removed or restructured to make it consistent with the system requirements. If the code is necessary, the test plan must be modified to make the test plan consistent with the original system requirements. In some cases, failure of test cases to cover all machine code reveals inaccura- cies or inconsistencies in the original system requirements. In this case, the original system requirements must be revised. A complete traceability audit trail must be maintained at all times. Note that the traditional Java execution model is entirely inconsistent with this requirement for traceability from source code to machine code. Traditional Java virtual machines hide the translation of byte code to machine code within a JIT compiler that is part of the run-time environment. Some sophisticated vir- tual machines actually produce multiple native-code translations for each byte-code method, optimizing the code differently in each translation based on run-time profiling information. The safety-critical Java profile supports deterministic compilation, linking and initialization. The entire safety-critical application is translated to native machine code and linked into a ROM-load- able image prior to execution. Since this technology is designed to support safety-critical development, tools will facilitate mappings between machine code and the corresponding source code. When measured in terms of RAMS objectives, the draft safety-critical Java specification offers important benefits over al- ternative approaches based on C, C++, traditional Java and RTSJ Java. Commercial availability of the proposed safety-critical Java standard to developers of safety-critical systems will enable eco- nomical creation of high-quality hard real-time software that sat- isfies the RAMS objectives discussed in this article. Aonix Tucson, AZ. (520) 991-6727. [www.aonix.com]. Download the free demo software proven in over 70,000 systems at... www.kuka-controls.com The Americas • Asia Pacific • Europe © 2006 KUKA Controls GmbH. All rights reserved. Trademarks are property of the respective owners. It’s easy! Deliver the benefits of hard real-time control plus high-end graphics, connectivity and access to all Windows applications on your next system. Our nonproprietary, real-time extensions – CeWin® and VxWin® – enable Windows® CE or VxWorks® to co-exist with Windows XP on a single computer. The hard real-time capabilities of the RTOS are not affected by Windows XP running simultaneously. And programming is easy using well-known, proven tools. Additional control hardware or costly intelligent co-processor boards for visualization are unnecessary. ”I need hard real-time performance at the lowest possible cost.” ”My customer wants high-end graphics, connectivity and a familiar interface!” Why not run any Windows®XP application with Windows®CE or VxWorks®? KUKA Controls GmbH Tel: 714-505-1485 • Fax 714-505-1149 Tel: 248-844-0569 • Fax: 248-844 -0505 Tel: +49 751 56122-0 • Fax: +49 751 56122 22 Sales@kuka-controls.com New! Multiprocessor, Hyper-Threading and APIC support.
Products&Technology 58 April 2006 6U cPCI SBC Targets Comm, Networking Onboard compute resources along with flexible, comm-specific I/O make an SBC well suited to communications, telecomm and networking applications, such as gateways, routers, switches and base stations. The new 6U single-slot CompactPCI D5 PowerPC SBC from Men Micro has all of this, and it operates in harsh environments from 0° to 60°C. Based on the PowerQUICC III, the D5 features either the MPC8540 or MPC8560 CPU, dissipating only 7 to 8W. The MPC8560 features several interfaces specific to telecomm systems, such as ATM, E3/T3 and HDLC. I/O in- cludes two slots for PMC mezzanine cards that support both front- and rear-panel connectors, and a 32/64-bit, 33/66-MHz PCI- to-cPCI bridge. An onboard Altera Cyclone FPGA is included for implementing several functional cores that are avail- able as rear-panel I/O. Up to 4 Gbytes of ECC DDR SDRAM main memory and 1 Gbyte or more of NAND flash memory are included for program or data storage. Two Gigabit Ethernet ports and one Fast Ethernet port are implemented as rear connections. Comprehensive BSPs are available for Linux, VxWorks and QNX as well as MEN’s own BIOS for PowerPC processors, MENMON. Pricing starts at $2,154 for single units. Men Micro, Lago Vista, TX. (512) 267-8883. [www.menmicro.com]. Dual MPC7448 PrPMC Targets ATCA Telecom Apps High-performance computing and telecom applications utilizing ATCA carrier cards need a lot of concentrated processing power. With that in mind, Extreme Engineering So- lutions has introduced the XPedite6200, a dual-proces- sor MPC7448 PrPMC sym- metric multiprocessing (SMP) platform. Several ATCA carrier cards can host up to four XPedite6200s, providing eight total PowerPCs in a single ATCA slot. The XPedite6200’s dual Freescale 7448 PowerPCs operate at up to 1.4 GHz. The Marvell MV64460 Discovery III chipset has a frontside bus speed of up to 133 MHz. Memory provided is up to 1 Gbyte of DDR SDRAM operating at up to 266 MHz and up to 128 Mbytes of flash. A 64-bit, 133 MHz PCI-X bus interface is provided. PTMC P14 I/O supports PTMC Configuration 5 Ethernet. A front panel Bellcore 1089- compliant Ethernet port is available for development or craft port usage in the field. Operating temperature is 0° to 70°C from a 3.3, 5 or 12V power supply. A Linux Support Package (LSP), VxWorks Board Support Package (BSP) and QNX BSP are available. OEM volume pricing is be- low $2,000 depending on volume, memory and processor configuration. Extreme Engineering Solutions, Madison, WI. (608) 833-1155. [www.xes-inc.com]. PC/104 Module Has Eight Software-Configurable Serial Ports A new PC/104 board offering complete software configurabil- ity, the Emerald-MM-8P from Diamond systems is designed to work in PC/104-expandable embedded computer systems running Linux, Windows, QnX, VxWorks and DOS. Each of the eight serial ports can be individually selected for RS-232, RS-422 or RS-485 (both local echo and no echo) under software control. I/O addresses and interrupt levels are also programmable, with interrupt sharing available for any number of ports. Each port may further be enabled or disabled in soft- ware. All configuration data is stored in an onboard EEPROM and is loaded automatically on power-up. A utility program shipped with the board can be used to configure all options and store the configuration to the EEPROM. For applications where fixed ad- dresses are desired, four groups of pre- set addresses are available with jumper settings that override the programmed settings. The Emerald-MM-8P offers eight digital I/O lines. The direction of each line is independently program- mable. Two I/O headers are provided, with four serial ports and four digital I/O lines on each header. The board operates on +5V only and is further tested and guaranteed for reliable operation over the extended temperature range of -40° to +85°C. Single unit pric- ing starts at $250. Volume discounts apply. Diamond Systems, Mountain View, CA. (650) 810-2500. [www.diamondsystems.com]. Wireless USB Reference Design Kit Aims at Ultrawideband Designers of WiMedia-based ultrawideband (UWB) systems will get a boost from a new reference de- sign kit based on Certified Wireless USB from the USB Implementers Forum. The reference design, in the form of a PCI Express mini card, incorporates WiQuest’s WQST110/101 ultrawideband chipset, which can be used to build complete device wire adapter or host wire adapter solutions. The reference design kit contains hardware and software, includ- ing schematics, layout source files, a detailed bill-of-material and de- sign and user manuals. Depending upon the configuration, the software package includes drivers and/or firmware for a host wire adapter and/or a device wire adapter. It also includes a Windows-based utility that sup- ports device discovery, field upgrade functionality, comprehensive diag- nostics and the newly defined wireless USB association models. When coupled wi
April 2006 59 Get Connected with companies and products featured in this section. www.rtcmagazine.com/getconnected Get Connected with companies and products featured in this www.rtcmagazine.com/getconnected LAN Controller Integrates Networked TFT LCDs Without a Client PC A LAN controller board with Ethernet interface now makes it pos- sible to integrate a wide range of TFT LCDs over a LAN or WLAN net- work without the use of a Client PC. The AristaNET controller board from Apollo Display Technologies reduces overall system costs, pro- vides Ethernet speeds of 10/100 Mbits/s, supports LCD resolutions from QVGA (320 x 240) to WXGA (1366 x 768), and supports wireless local area networks up to 802.11 b/g—54 Mbits/s. It supports TFT LCDs from 5” to 46” diagonal in size, comes with an integrated 4-wire resis- tive touch screen controller, integrates in LAN/WLAN networks, and supports a range of graph- ics formats, including BMP, JPEG, GIF and PNG. Network configura- tion of ArtistaNET is over dynamic host configura- tion protocol (DHCP), with configuration over the Web browser surface. Control is possible over network sock- ets (independent from the op- erating system). Aside from reducing cost, the ArtistaNET makes tem- perature-sensitive applications like hermetically sealed human-machine interfaces and in-wall mounting possible. Targeted applications include IP65 ingress protection, electronic door plates and posters, POI/POS displays, HMIs for machine control, and status displays to name a few. Pricing is $144.75 in production quantities of 10K units. Apollo Display Technologies, Ronkonkoma, NY. (631) 580-4360. [www.apollodisplays.com]. ATCA SBC with New Dual-Core Xeon LV 2.0 GHz An AdvancedTCA single board computer offers two Dual-Core In- tel Xeon processors LV 2.0 GHz and up to 8 Gbyte DDR-2 400 SDRAM with ECC. The ATCA-7820 from GE Fanuc is fully compliant with the PICMG 3.0/3.1 specification, and combines an AMC.1 Type 8S expan- sion site as well as a PCI-X PMC expansion site to create a powerful and I/O-diverse platform. Also included are the Intel E7520 Memory Con- troller Hub and Intel 6300ESB I/O Controller Hub, which provide high bandwidth for increased memory capacity, and high I/O throughput. The new multicore processors combine performance with power management capabilities to help implement new features in a wide range of communications applications, particularly in AdvancedTCA form- factor designs. Additional features include an option for an onboard 2.5-inch IDE hard drive (up to 80 Gbytes), a single 10/100 Mbit Ethernet port and dual USB 2.0 connections out the front panel. There are also “user” zone connections for dual RS-232, 32-bit/33 MHz PCI bus, dual USB 2.0 and mouse/keyboard support as well as support for an AMC.3-compliant serial ATA module using the AMC site. Single unit pricing starts at $5,995. GE Fanuc, Huntsville, AL. (800) 322-3616. [www.gefanuc.com/embedded]. Tiny Industrial Device Server Simplifies Factory Connections Most factory and building environments were not designed with network connectivity in mind, making it difficult and expensive to later add networking infrastructure. But as the number of networked fac- tory and building automated systems continues to grow, the cost and complexity of connecting equipment to enterprise systems is rising. The small, ruggedized XPress DR+ industrial device server from Lantronix was designed to simplify this process by cascading multiple devices from a single networked connection. The 3.45-in. x 2.25-in. x 4.85-in. XPress DR+ incorporates SwitchPort+, which converges Ethernet switch technology with Lantronix device networking technology to extend the network, of- ten without adding infrastructure. Previously out-of- reach machines can be connected and remote firmware upgrades are enabled. The unit supports industrial protocols such as Modbus TCP, Modbus ASCII, Modbus RTU and DF1 and includes an auto MDI/MDIX Ethernet interface. The XPress DR+ supports two serial ports and two 10/100 Ethernet ports in a rugged Din-rail case. A wide operating temperature range of -40° to +70°C, combined with 15KV serial ESD protection and 2.5KV Ethernet isolation, help safeguard the unit in harsh industrial environ- ments. Options include 9-30 VDC and 9-24 VAC power inputs. Pricing is $399 for a single unit. Lantronix, Irvine, CA. (800) 526-8764. [www.lantronix.com]. 108 Watt Power Supply +3.3V, +5V, +12V and -12V DC output 6V to 40V DC input range High efficiency up to 95% Extended temperature: -40OC to +85OC 1.800.665.5600 www.tri-m.com info@tri-m.com tel: 604.945.9565 fax: 604.945.9566 108 Watt PC/104+ Power Supply HE104+DX
60 April 2006 Products&Technology Smart I/O Module Controls up to 8 SSRs A new SSR I/O module monitors and controls up to eight standard SSRs. Each SSR socket in the Sensoray 2652 may be populated with either an AC in, AC out, DC in SSR or a DC out SSR. I/O services to a Sensoray 2601 communication module enable remote Ethernet clients to monitor and control the SSRs. A single Category-5 UTP cable carries microcontroller power and communication signals. The 2652 applies a 10 millisecond software debounce filter to all input SSRs. Each output SSR may be controlled explicitly by the client, or it may operate as a PWM output with a client-specified rate and duty cycle. Five independent interlock circuits allow external circuitry to unconditionally de-energize an output SSR. Onboard, finger-safe con- nectors enable direct connections to field wiring. Two connectors are provided for each SSR, one for the line con- nection and one for the load. The module supports up to five inde- pendent interlock circuits that supply interruptible voltages through safety contacts. Each output SSR is shunt-configured to derive its logic power from one of the interlock circuits. Two connectors are provided for the interlock cir- cuits. One connects to the interlock voltage sources, and the other may be used to pass through the interlock voltages. Price for a single unit is $213. Sensoray, Portland, OR. (503) 684-8005. [www.sensoray.com]. Ruggedized 3U CompactPCI Gigabit Ethernet Switch/Router Designed for implementing system-wide Intra-Platform Networks (IPNs) in weight- and space-constrained environments, a new 3U CompactPCI (cPCI) Gigabit Ethernet (GbE) switch/router is available in both air-cooled (SCP) and con- duction-cooled (DCP) configura- tions. The SCP/DCP-681 Compact SwitchBlade from Curtiss-Wright Controls Embedded Computing is a 10-port, fully managed, intel- ligent multilayer card that provides up to ten wire- speed 10/100/1000 Mbit/s Ethernet interfaces in a single 3U cPCI slot. The SCP/DPC 681 design provides wire-speed, non-blocking per- formance on all ten (10) of its 1 GbE ports over the cPCI backplane. With address tables and buffer memory fully integrated on chip, the board can support full-duplex end-to-end flow and congestion control that facilitates reliable operation. The SCP/DCP-681 supports CLI, Telnet, Web and SNMP manage- ment interfaces that can be used to configure a complete set of protocols and parameters including PBIT, IBIT, CBIT, Layer 2 protocols, Layer 3 (IPv4/v6) protocols, Multicasting, QoS and Security. Curtiss-Wright also offers an optional 3U cPCI rear transition module that can be used to connect end nodes using standard RJ45 cables. DCP (conduction- cooled) versions of the card can also be supported with an optional 10- port LEDS front-panel plug-in. Pricing starts at $9,100. Curtiss-Wright Controls Embedded Computing, Leesburg, VA. (703) 779-7800. [www.cwcembedded.com]. VITA 46 Chassis Has 12-Slot Mesh Backplane The upcoming VITA 46 and VITA 48 standards, being developed and defined by the VITA Standards Organization (VSO), will define the next major evolutionary advance in open architecture, standards- based embedded computing. A new VITA 46 chassis has been devel- oped by Elma Electronic with a 12- slot mesh backplane. The Elma Electronic VITA 46 ATR chassis features integrated front- to-rear airflow. It uses 120 VAC or 28 VDC power supplies with bottom patch panel access to the P2 section of the backplane. The Elma Bustronic 12-slot VITA 46 hybrid fabric backplane is a general-purpose VITA 46 implementation that sup- ports three legacy VME64x slots and nine VITA 46 slots. The VITA 46 bus segment provides two 4-slot meshed clusters for high-performance blade computing or pipeline graphics processing. The VMEbus origi- nates in the 3-slot legacy VMEbus segment and is continued across the P2 connectors of the VITA 46 bus segment. The high-density MultiGig connectors in each slot have been in- terconnected so that each of the two 4-slot clusters provides a choice of star, mesh or ring topologies. Pricing for the VITA46 ATR starts at under $4,500, depending on volume and features. Lead time is 6 weeks ARO. Elma Electronic, Fremont, CA. (510) 490-7388. [www.elmabustronic.com]. Mezzanine Supports 5 Simultaneous Video Inputs For high-performance video-intensive applications such as mission computers and surveillance systems, the ability to generate real-time 3D terrain visualization is often accompanied by the need for multiple video channels. A video input mezzanine card from Radstone Embed- ded Computing supports five simultaneous video inputs—two RGB, two TV and one DVI—with video input resolutions of up to SXGA (1280 x 1024) and digital video input resolutions up to UXGA (1600 x 1200). Designed to complement the Octegra3 video and graphics proces- sor, the VIM2 Video Input Mezzanine card features 539 Mbyte/sec ag- gregate digitized video bandwidth, up/downscaling of video inputs with pr
April 2006 61 Get Connected with companies and products featured in this section. www.rtcmagazine.com/getconnected Products Get Connected with companies and products featured in this www.rtcmagazine.com/getconnected FPGA Board Performs Image Processing 10-15x Faster than PowerPC Platforms Combining high-density FPGAs, an onboard switched fabric, Pow- erPCs and PMC interfaces, a new embedded platform performs high- speed I/O and image processing in a single slot. The PowerRACE-3A carrier card from TEK Microsystems is targeted at complex image pro- cessing applications such as UAVs or advanced industrial inspection. The unit can reduce system board count by up to 40 percent with cor- responding reductions in weight, power, volume and cost. The PowerRACE-3A uses two 800 MHz 440GX PowerPC pro- cessors to support high throughput without incurring host processor overhead. An onboard fabric allows each PMC site to transfer data concurrently to off-board RACE++ ports, FPGA processing or to memory, thereby eliminating fabric contention and maximizing overall system performance. The carrier can be configured with any one of the more than 30 available TEK Microsystems PMC modules. Included is the tekX software environment, which provides tools for fabric configuration, buffer management, data transfer, inter- processor communications, data storage/playback and integration of streaming FPGA and I/O modules. TekX reduces system development by using a common API to shield the developer from the complexities of the fabrics and the hardware. The tekX environment supports all cur- rent PowerRACE models and will support integration of future products without application changes. Single unit pricing starts at $17,995. TEK Microsystems, Chelmsford, MA. (978) 244-9200. [www.tekmicro.com]. System Host Boards Feature One or Two Dual- Core Processors A new pair of system host boards from Trenton Technology offers single or dual dual-core processors. The SLT is a dual dual-core proces- sor, server-class system host board (SHB) that represents the latest addition to Tren- ton’s line of SHB Express or PICMG 1.3-compatible products. The Trenton SLI is a single dual-core processor ver- sion of the SLT. The high-bandwidth/ high-speed PCI Express (PCIe) links designed into the SLT/SLI are suited to sup- port multiple PCI Express cards, devices and bridges to PCI-X/PCI op- tion cards on a PICMG 1.3-compatible backplane. Trenton’s SLT features the Dual-Core Intel Xeon Processor LV 2.0GHz. The SLT/SLI products feature a 667 MHz front side bus, and the new processors have 2 Mbytes of L2 shared cache. The Intel E7520 chipset configuration on the Trenton SLT/SLI boards provides a dual- channel DDR2-400 memory interface capable of supporting 8 Gbytes of memory with a maximum memory bandwidth of 6.4 Gbytes/s. Edge connectors on the SHBs provide two x8 PCI Express links, one x4 PCI Express link and five PCI Express reference clocks on edge connectors A and B. Other SLT/SLI board features include dual SATA/150 in- terfaces, quad USB 2.0 connections, dual 10/100/1000Base-T Ethernet ports, onboard video and an optional I/O expansion board for legacy I/O support. Representative pricing for the dual-processor SLT is $3,775, and for the single-processor SHB is $2,750. Trenton Technology, Atlanta, GA. (770) 287-3100. [www.TrentonTechnology.com]. Open Source IPC Technology for Distributed Systems A scalable, high-performance interprocess communications ser- vice for distributed systems utilizing multiple operating systems is able to scale from DSPs and microcontrollers to 64-bit CPUs. LINX from Enea is available for evaluation on Enea’s OSE RTOS and on Linux now, and can be readily ported to other operating systems. Enea will offer the new IPC service as open source to Linux developers. LINX message-based IPC technology greatly simplifies the design of complex, heterogeneous distributed systems utilizing multiple operat- ing systems and processors. LINX is platform- and media/interconnect- independent. It is also transparent, enabling application processes running on multiple CPUs and operating systems to communicate with each other as if they were running on the same CPU under the same operating system. This transparency makes it easy to distribute LINX-based ap- plications across multiple processors and operating systems. It also makes systems easy to scale and reconfigure with little if any change to the application code. Later this year, Enea will announce a number of enhancements to LINX, including a naming service (publish/subscribe), reliable multicast, au- tomatic failover to redundant links, automatic byte ordering (Endian conversion) and security/encryption. Enea will make the Linux version available for free as open source under a dual BSD/GPL license. Produc- tion release is scheduled for June. Enea, San Jose, CA. (408) 383-9480. [www.enea.com]. Total Power: 168 Watt with ATX Interface +3.3V, +5V, 12V output 6V to 40V DC input range Extended
April 2006 63 Virtual Platform Available for TI’s OMAP 3 Platform New classes of mobile multi- media devices incorporate imaging, audio, video and productivity appli- cations, based on a multitude of dif- ferent technologies. Engineers de- signing converging mobile phones with advanced video and imaging technologies need to build and test software for their systems early in the development process. Now they can with Virtio’s VPOM-3430 Vir- tual Platform for the Texas Instru- ments OMAP 3 architecture. The VPOM-3430 Virtual Platform provides a complete simulated environment for the OMAP3430 hardware and software platform, and lets designers take advantage of the new multimedia technologies in- troduced in the OMAP3430 processor before silicon is available. The OMAP3430 processor is the industry’s first applications processor based on the ARM Cortex-A8 superscalar architecture, which delivers triple the performance of the ARM11 core in OMAP 2 processors. The advanced IVA 2+ accelerator will boost video, imaging and audio per- formance of the device. The VPOM-3430 Virtual Platform simulates all of these technolo- gies and supports TI’s M-Shield security framework enhanced with ARM TrustZone technology, which provides a secure hardware foun- dation for security applications. Virtio’s VPOM-3430 Virtual Platform starts at $2,488 for a single user license. Virtio, Campbell, CA. (408) 341-0844. [www.virtio.com]. Get Connected with companies mentioned in this article. www.rtcmagazine.com/getconnected Get Connected with companies mentioned in this article. www.rtcmagazine.com/getconnected Get Connected with companies and products featured in this section. www.rtcmagazine.com/getconnected Ad Index End of ArticleProducts Get Connected with technology and companies providing solutions now Get Connected is a new resource for further exploration into products, technologies and companies. Whether your goal is to research the latest datasheet from a company, speak directly with an Application Engineer, or jump to a company's technical page, the goal of Get Connected is to put you in touch with the right resource. Whichever level of service you require for whatever type of technology, Get Connected will help you connect with the companies and products you are searching for. www.rtcmagazine.com/getconnected Get Connected with technology and companies providing solutions now Get Connected is a new resource for further exploration into products, technologies and companies. Whether your goal is to research the latest datasheet from a company, speak directly with an Application Engineer, or jump to a company's technical page, the goal of Get Connected is to put you in touch with the right resource. Whichever level of service you require for whatever type of technology, Get Connected will help you connect with the companies and products you are searching for. www.rtcmagazine.com/getconnected Get Connected with companies and products featured in this section. www.rtcmagazine.com/getconnected RoHS-Compatible SBC Features Energy-Efficient CPU A RoHS-compatible SBC features low power consumer of 0.9 watts and has built-in encryption and 2D graphics. The IP-06060 form WIN Enterprises utilizes the AMD Geode LX 800@0.9W processor running at 500 MHz. The WIN SBC is 5.7” x 4”, and is designed to complement the AMD Geode processor with a SATA interface, VGA/LCD capability, two 10/100 LAN ports, audio and SSD. The AMD Geode LX 800@0.9W processor is energy efficient and designed for use in small computers, set- top boxes, TVs, handhelds and consumer electronics devices. As an x86-based processor, it will run the vast available library of conventional software. Additional features of the new board include total power consumption of the SBC of 15W, a VIA VT6421A SATA RAID Controller, one DDR SO-DIMM for up to 1 Gbyte memory, a CRT/TFT interface and AC 97 audio. Pricing starts at $254. WIN Enterprises, North Andover, MA. (978) 688-2000. [www.win-ent.com]. 35 Watt capability 6V to 40V DC input range Supports up to 8 digital temperature sensors RS232 serial port / Opto-coupled inputs 750mA-Hr Battery Backup 1.800.665.5600 www.tri-m.com info@tri-m.com tel: 604.945.9565 fax: 604.945.9566 5V Vehicle Power Supply & Battery Pack V5SC
April 2006 65 IndustryWatch A Delegation RTOS Can Slice Low-Value (Boring) Work from Real-Time System Projects Burdening an RTOS with long and unpredictable routine work like graphical interface and file system can make ensuring real-time behavior difficult. It is better for the RTOS to delegate those tasks to a client operating system and concentrate on real-time performance. by Victor Yodaiken FSMLabs E ven though a delegation RTOS model for Linux has been used in production systems for a decade, the underlying programming model is still somewhat controversial. In this model, programs run on a relatively Spartan hard real-time POSIX kernel with the capability of running Linux or BSD or any other suitable operating system as a preemptible client. This design does not absolutely require programmers to change how they work: conventional RTOS applications can run unchanged over compatibility layers and, as with most modern systems, it is even possible to generate code automatically from UML or MatLab models without any programming at all. Programmers and system architects who want to directly take advantage of the double kernel, however, adopt a style based on “delegation.” The idea is to strip real-time code down to es- sential elements and to delegate non-real-time functionality to the client environment. Programs are divided into real-time and non-real-time modules: the real-time modules are as simple as possible to improve reliability, while complex user interfaces and back-end computing are pushed into the client environment. Products employing delegation in application software in- clude a hardware-in-loop simulator/test system developed at Pratt & Whitney (Figure 1), a software-defined radio from Harris, aerospace and automotive diagnostic systems, Juniper Network’s J-series router and many robotic systems (Figure 2). The P&W application relies on PC workstations, servers and even laptops to control extensive VME-based test equipment, and makes use of memory-protected real-time threads and real-time networking Get Connected with companies mentioned in this article. www.rtcmagazine.com/getconnected Get Connected with companies mentioned in this article. www.rtcmagazine.com/getconnected Get Connected with companies and products featured in this section. www.rtcmagazine.com/getconnected Ad Index End of ArticleProducts Get Connected with technology and companies providing solutions now Get Connected is a new resource for further exploration into products, technologies and companies. Whether your goal is to research the latest datasheet from a company, speak directly with an Application Engineer, or jump to a company's technical page, the goal of Get Connected is to put you in touch with the right resource. Whichever level of service you require for whatever type of technology, Get Connected will help you connect with the companies and products you are searching for. www.rtcmagazine.com/getconnected Get Connected with technology and companies providing solutions now Get Connected is a new resource for further exploration into products, technologies and companies. Whether your goal is to research the latest datasheet from a company, speak directly with an Application Engineer, or jump to a company's technical page, the goal of Get Connected is to put you in touch with the right resource. Whichever level of service you require for whatever type of technology, Get Connected will help you connect with the companies and products you are searching for. www.rtcmagazine.com/getconnected Get Connected with companies and products featured in this section. www.rtcmagazine.com/getconnected Figure 1 Joint Strike Fighter engine being tested under RTLinux control.
IndustryWatch 66 April 2006 to connect to reflective memory and non-real-time networking to connect control machines to operators. The Harris example runs on quad-processor VME boards so that it can find the compute power needed to process waveforms. A diagnostic machine for the Joint Strike Fighter runs on very low power system-on-chip processors and uses real-time Firewire 1394 drivers. Juniper’s J-series routers replaced ASICs with real- time software coordinating with tasks under BSD Unix. Motivating the Design Before we came up with the idea of delegation program- ming, we spent a great deal of time studying large embedded software projects and trying to figure out why they took so long, involved so much repetition and were so prone to failure. The desire to avoid the not exactly thrilling work of yet another boot loader, or drivers for storage devices and other similar tasks, provided much of the motivation for the design. As operating system developers, we also wanted to avoid re-implementing ca- pabilities that were already available in standard operating sys- tems. Networking stacks, efficient file systems, standard APIs and many other useful services solved problems in the desktop/ server world, but seemed to be ongoing projects for embedded programming. Finally, we were unhappy with the fragility of real-time scheduling. It is not unusual for embedded development projects to flounder on timing issues that only became apparent after the application was nearly completed and the full system load was in place. In many cases, low priority non-real-time services in- terfere with critical software in ways that are difficult to predict or to design around. Shared resources, like file systems, schedul- ers and internal operating system data structures produce inter- actions between critical and non-critical tasks that are difficult to predict, difficult to find on test and difficult to work around. Even for so-called soft real-time applications, as the application gets closer to release, timing can degrade past acceptable lim- its. In fact, “soft real-time” is too often synonymous with “fails under load.” How It Works In brief, the idea is to get beyond the limitations of the con- ventional by turning commodity client operating systems into board support packages (BSPs). The underlying technology is conceptually simple. A POSIX threads-based real-time kernel hooks itself to the client operating system via a virtual machine interrupt controller. Client commands to disable and enable in- terrupts are intercepted by the virtual machine. When the client asks for interrupts to be disabled, the virtual machine obliges by pending non-real-time managed hardware interrupts until the client asks for interrupts to be re-enabled. In the meantime, inter- rupts managed by real-time software are not impeded and pass through to real-time handlers and schedulers without delay. The real-time scheduler is completely separate from the cli- ent scheduler and there are no hidden shared resources. As a re- sult, the real-time side and the client are decoupled from each other in normal operation. Communication takes place through specialized mechanisms—shared memory, fifos, non-locking queues and even higher level XML/RPC and CORBA connec- tors—all designed so that real-time code will never be involun- tarily blocked by non-real-time software (Figure 3). On a 64-bit multi-core AMD Opteron, this model provides a worst-case interrupt latency under 4 microseconds, and on a 100 MHz Arm9, worst-case interrupt latency is under 25 micro- seconds—no matter how much load is put on the Linux services. One of the ways we quantify real-time behavior is with a “jitter- test.” The jitter test creates a single real-time thread that asks to be awakened every millisecond, and compares expected wake time to actual wake time. During the jitter test, we put heavy and varying loads on the system: network, compiles, network file transfers, graphical operations and so on. Figure 2 An RTLinux-powered automobile diagnostic system for DaimlerChrysler. This device was based on Bright Star Engineering’s AMD AU processor boards and had low power requirements. Non real-time applications and utilities Protected memory Real-time threads Client Operating System and Drivers RTCore and RTCore Standard threads and handlers Interrupt Virtual Machine Processor and Devices Figure 3 Basic RTCore system architecture.
IndustryWatch April 2006 67 For example, I have a relatively low-end commodity Pentium- 4 workstation sitting under my desk that has been running a jitter test for the last four weeks—while being used as a backup server, a host for tests of our Eclipse-based IDE, a development worksta- tion and also as the target for ping-floods and other attacks. The workstation reports worst-case jitter time at 28 microseconds— reasonable but not outstanding. On our current record holders, 64-bit Opterons, we cannot find a way to push the number over 8 microseconds. Since jitter seems to be mostly a result of memory and bus contention, we expect to see significant improvements in the next years as those technologies are improved. In the meantime, soft- ware methods such as processor reservation (preventing the cli- ent from using a processor on a multiprocessor system) and timer advance (trading throughput for precision by pre-triggering timer events) can further reduce jitter times when necessary. Peripheral device makers, chip vendors and independent software vendors in the desktop/server markets are willing to make sure standard operating systems, like Linux and BSD, sup- port their products. The customer base of the standard operating systems is so huge compared with the markets for embedded op- erating systems that it is worth the expense for vendors to make their products compatible and to provide any needed drivers and other software support. We don’t have to create boot loaders, fix the TCP/IP stack, wrestle with support for special instruction sets, struggle with multiprocessor support or write non-real-time drivers for Linux or BSD—because someone else has already had a compelling reason to do the work and release the result. The comprehensive Linux and BSD networking stacks, which offer excellent implementations of everything from simple IP to PPOE and IPSEC and IPV6, can be invoked through helper processes on the client side. The same applies to file systems and middleware. Client drivers run unmodified, so supported hard- ware is easy to find. And since new processor technologies—ev- erything from multicore to specialized instruction sets—are rapidly supported in Linux and BSD, keeping up with hardware advances is simplified. The Eclipse IDE, Carrier Grade Linux (CGL) and the many Linux and BSD boot loaders also become available when we make use of Linux and BSD clients. Obviously, some customization and quality assurance still need to be done, but the difference in effort is significant. For example, several times we have stream- lined the boot process for Linux systems so that the system will come up in under one second. Starting with a working boot loader, bus initialization and collection of device drivers is much more cost-effective and much easier to refine into a repeatable process than starting from scratch. Similarly, modifications to the Eclipse IDE have been orders of magnitude less effort than it would have been to develop an IDE from scratch. Cost-effective software development depends on software re-use more than anything, and a split-function OS on top of Linux with good communications invites developers to re-use practically anything that runs in the Linux/BSD environment or can be connected to that environment. As an example of the latter, consider connecting Internet Explorer or even Microsoft Excel to a control a real-time application via XML/RPC and TCP/IP. Two Programming Examples To get a sense of how programs are built, consider a sim- ple data acquisition application. The real-time part might need to sample a sensor at some fixed rate. The code for that would create a thread that might look as simple as the loop in Figure 4. This code would be built under the make system provided with FSMLabs’ RTLinux to generate a Linux executable—call it “getdata.rtl.” To run it and store the output in a file, we’d use a command line “getdata.rtl > mylogfile.” Note that Linux has a default journaling file system. To switch to a flash file system is a matter of reconfiguring Linux. To send the data to a back-end processing application before storing it, we change the command line to “getdata.rtl | mybackend _ processing > mylogfile.” The output can be sent out over a network to a port can be done by using the standard netcat program. The example below sends data using TCP to port 1200 of the destination machine with some encryption of the data on the way out—Linux even has standard encryption programs that could be used as well. As you can see from this example—“getdata.rtl | myencrypt | netcat remotelog.com 1200”—the real- time code doesn’t need to worry about data storage, back-end processing or network connectivity. All of those functions are delegated to the non-real-time client environment. An emulation of VxWorks also illustrates how delegation works. In the emulation library, real-time functions such as thread creation, semaphores and mutex operations and timers are implemented by calls to the
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April 2006 69 IndustryWatch You Don’t Have to Stop High-Availability Systems for Updates Object-Oriented Programming Languages and Dynamic Plug-ins can dynamically upgrade the functionality of running systems. by Pat Rogers and Cyrille Comar AdaCore D evelopers typically want to modify, enhance or correct parts of high-availability applications without having to bring the entire system to a halt, re-build and re-boot. Us- ing current operating systems, new code can be loaded on de- mand through dynamically loaded/linked libraries (DLLs) on Microsoft’s Windows, or through “shared libraries” on Unix- based operating systems. In practice, however, the protocol for invoking routines in a DLL or shared library is very low level and is therefore not ideal for mission-critical applications. In contrast, object-oriented (OO) programming languages offer a much more attractive ap- proach to the problem by using the more robust, high-level proto- col of dynamic dispatching to invoke operations in dynamically loaded “plug-ins.” Plug-ins contain instances of new subclasses in the inheritance “tree,” that is, instances of subclasses inherited from the superclasses known to the application. A plug-in is thus type-safe, robust and enriches the functionality of the original application without requiring execution to stop. Ada, originally developed for embedded and real-time ap- plications, was in fact the first internationally standardized OO language in 1995. Ada is widely used in high-integrity applications with very static application characteristics, but the language can also be used in the more dynamic context of high availability. Ada’s main programs can use the DLL or shared object facility to load the plug-ins, and can then use dynamic dispatching at the application level to transparently invoke routines provided by the plug-ins. A simplistic simulation of the instruments on an automo- tive dashboard illustrates how new functionality can be added at run-time without stopping the execution of the application. The system is developed in a way that makes it completely and con- veniently portable to operating systems as different as Windows, Linux, Unix or VMS. The instruments on the dashboard are coded as separate plug-ins, independent of the main program. They are loaded at run-time such that the simulation can take newly created instru- ments into account without having to be restarted. Although stand-alone, these plug-ins share objects and code in the original program. They become part of the original program through dy- namic linking (Figure 1). Abstract Base Class The common code base is shared by the application. The plug-ins and all foundation classes are declared in this part of the application. The most important of these foundation classes is “Instrument,” which defines the abstract base class for the subclasses defined by the plug-ins (Figure 2). In Ada, a class is represented by the combination of individual building blocks rather than by the single class construct of some object-oriented languages. Specifically, a class is represented in Ada by a type, declared within a package, with subprograms that manipulate ob- jects of that type. The package provides the encapsulation and the subprograms provide the operations. These building blocks work together as a whole, however. Only those subprograms that are declared in the package with the type and that manipulate objects of the type are inherited by any subclasses. The package “InDash” illustrates these concepts. Without going into the full details, the package first exports a number of declarations to client code, including the type “Instrument” and operations that manipulate objects of that type via param- eters. There follows a “private part” that encapsulates the type’s representation; as a result client code can use the type to create instances but cannot access the internal implementation of those instances. This private part of the package in Code Segment 1 corresponds to the “protected” part of a C++ class construct. Additionally, any instrument instance (including instances Get Connected with companies mentioned in this article. www.rtcmagazine.com/getconnected Get Connected with companies mentioned in this article. www.rtcmagazine.com/getconnected Get Connected with companies and products featured in this section. www.rtcmagazine.com/getconnected Ad Index End of ArticleProducts Get Connected with technology and companies providing solutions now Get Connected is a new resource for further exploration into products, technologies and companies. Whether your goal is to research the latest datasheet from a company, speak directly with an Application Engineer, or jump to a company's technical page, the goal of Get Connected is to put you in touch with the right resource. Whichever level of service you require for whatever type of technology, Get Connected will help you connect with the companies and products you are searching for. www.rtcmagazine.com/getc
IndustryWatch 70 April 2006 of subclasses, which are of course also instruments) can display its current state and can have that state updated. State updates are based upon the passage of some number of milliseconds. For the sake of comparison, consider the roughly corre- sponding C++ class declaration in Code Segment 2. We see that the Ada type corresponds partly to the C++ class construct and that the Ada package construct corresponds partly to a C++ namespace, except that the package also provides en- capsulation of the type’s implementation via the package “private part.” The procedures and functions that manipulate values of the type correspond to the C++ member functions. Ada routines manipulate these values via parameters, using either of two pos- sible syntactic forms for the calls. For example, given an object named Display, of type Any_Instrument, we could call the Set_ Name procedure using either the traditional functional notation: Set _ Name (Display, “Tach”); or the popular “distinguished receiver” syntax: Display.Set _ Name (“Tach”); The InDash package would also have a textually separate “package body” that implements the operations. This package body corresponds to the “private” part of a C++ class. We omit the package body here for the sake of brevity. Plug-in Subclass Instance Registry The code base also includes the single object representing all the instruments currently on the dashboard. Essentially, this object is a registry designating the instrument objects created by the plug-ins during plug-in loading. For example, the following is a fragment of another package, named “Dash_Board,” that con- tains the declaration of this registry object: package Instruments is new Ada.Containers.Vectors (Positive, InDash.Any _ Instrument); Registry : Instruments.Vector; Thus the registry is an object of the type (i.e., class) Vector provided by the instantiation of the standard “generic” package Ada.Containers.Vectors. A generic is simply a template for a program unit—in this case a template for a package—that can be tailored for specific types and other properties. In C++ generics are in fact referred to as templates, and the Ada Vec- tors generic is conceptually similar to a template provided by the C++ Standard Template Library (STL). In this case, the Vectors generic is tailored to contain access values (essentially pointers) that designate any kind of instrument. In effect this kind of vector contains “pointer to base class” values, to use C++ terminology, because such a pointer can designate any class in a set of classes related directly or indirectly by inheritance. This effect is achieved because the designated type is “class-wide,” as indicated by the syntax of the access type declaration within package InDash: type Any _ Instrument is access all Instrument’Class; The designated type named “Instrument Class” rep- resents this set of classes (types) related by inheritance, directly or indirectly, from type Instrument. The type Any _ Instru- ment is therefore the “pointer-to-base class” type that can des- ignate any subclass of Instrument. The registry contains these pointer values. Plug-ins call the Dash_Board.Register procedure for the objects they allocate locally within themselves, passing just such an access value as the parameter: procedure Register (Device : Any _ Instru- ment) is begin Registry.Append (Device); end Register; The instrument passed to procedure Register is simply ap- pended to the Registry object. You should note that the single Registry object is thus shared between the main program and all the plug-ins (Figure 1). Main Program Dynamically Linked Plug-In Dynamically Linked Plug-In Dynamically Linked Plug-In Instance Class Instance Class Class Class Instance Instance Registry Figure 1 The main program contains references to the instances registered by the dynamically linked plug-ins.
IndustryWatch April 2006 71 Main Program The main program iteratively discovers and loads any available plug-ins, displays the current dashboard and updates the states of the instruments according to how much time has elapsed. Any new plug-ins are discovered and loaded on each iteration so the number of instruments appearing in the dashboard can increase dynamically. Our discovery approach is uncontrolled and is, there- fore, not realistic, but suffices for this demonstration. Specifically the main program, via procedure Discover_Plugins, searches all the immediate subdirectories for DLLs and loads any new ones it finds. This behavior continues indefinitely, as the source code frag- ment in Code Segment 3 illustrates. The delay statement causes the main program to suspend (“sleep”) for the number of seconds corresponding to the number of milliseconds the user entered prior to the loop. We explain the other two routines’ calls next. Dynamic Dispatching to Instances within Plug-ins Procedures Dash_Board.Display and Dash_Board.Update, called by the main program, contain high-level dispatching calls from the main program to any plug-ins that have been discov- ered. Both procedures iterate over the internal Registry of ob- jects maintained by package Dash_Board and make dispatching calls to the operations defined by the subclass instances declared within the plug-ins. The body of procedure Display follows in Code Segment 4. The object “C” is of a type named Cursor (from package In- struments) that supports iteration over a composite data structure, in this case over the Instruments.Vector object named Registry. Initialization of the cursor sets it to indicate the first element con- tained within the Registry vector, if any such element is present. The loop will execute as long as elements remain in the Registry vector to be visited. The function Element returns the value at the specified cursor location, in this case a pointer value designating some kind of instrument object. The Display operation is applied to this designated object—the dereference is implicit—thereby dispatching to a Display routine specific to the type of designated instrument. These calls are dynamically dispatched at run-time because the specific types of designated objects are not known until the calls occur. This fact highlights the point that dynamic dispatching in Ada is a property of calls, not operations. That is why we do not need the C++ “virtual” reserved word preceding the Ada method declarations in the package. Any of those meth- ods can be a dispatching target. The call therefore dispatches from the main program to the operation defined within the plug-in, and it does so in a type- safe manner because the operation’s signature (the parameter and result type profile) is specified by an interface common to both Instrument #name: String +Display( ) +Update(Millisec:Integer) +Set_Name(To:String) +Name( ): String Digital_Speedometer #Value: Float +Display( ) +Update( ) +Display( ) +Update( ) +Display( ) +Update( ) +Display( ) +Update( ) Clock Accurate_Clock #Seconds: Integer #Hours: Integer #Minutes: Integer #Milliseconds: Integer Numeric_Gauge #Value: Percentage #Rate: Float Chronometer +Display( ) +Display( ) Graphic_Gauge Figure 2 The class diagram showing the abstract base class Instrument in the main program and concrete subclasses created by plug-ins.
IndustryWatch 72 April 2006 the plug-in and the main program. The fact that the object is of a type not necessarily in existence when the main program was compiled is completely transparent to both the programmer and the client main program. Indeed, transparent extension is the desired effect in this example. The Update procedure works in exactly the same manner but dispatches to the Update operation for each of the designated instrument instances. Plug-ins Subclasses Plug-ins are independent of the application in terms of de- pendencies and can be developed when the application is run- ning. Each plug-in defines one or more subclasses of the base instrument class, allocates instances of those subclasses and reg- isters them with the dashboard when the main program discovers and loads the corresponding DLL. The declaration of the speed- ometer plug-in is in Code Segment 5. Object-Oriented Programming Terms • An object encapsulates state and operations to manipulate that state. Objects are the fundamental building block of object-oriented programs • Encapsulation is restricting the com- pile-time visibility of an object’s imple- mentation. • Objects are individual instances of classes. • A class is an implementation of an abstract data type. As such, classes define the external interfaces and the internal state representation of in- stances. • Inheritance is the definition of a class by means of extending the implemen- tation and interface of one or more ex- isting classes. • A superclass is a class from which other classes are inherited. • A subclass is a class that is defined by inheritance from one or more super- classes. • Classes can be abstract, meaning that they primarily define interfaces for sub- classes to implement, rather than im- plement those interfaces themselves. • Polymorphism is the ability to treat a given object in terms of common inter- faces provided by inheritance, regard- less of the specific class of object in- volved. • Dynamic dispatching is another term for dynamic binding, in which the spe- cific operation invoked is not deter- mined until run-time. • The receiver is the object to which an operation is applied. • The distinguished receiver syntax refers to a syntax for invoking operations in which the receiver is specifically identi- fied: Object.Operation(parameters) Code Segment 1 with Ada.Strings.Unbounded; package InDash is type Instrument is abstract tagged private; type Any _ Instrument is access all Instrument’Class; function Name (This : access Instrument) return String; procedure Set _ Name (This : access Instrument; To : String); procedure Display (This : access Instrument); procedure Update (This : access Instrument; Millisec : Integer) is abstract; private use Ada.Strings.Unbounded; type Instrument is abstract tagged record Name : Unbounded _ String; end record; end InDash; Code Segment 2 #ifndef Instrument _ #define Instrument _ #include <string> using namespace std; namespace InDash { class Instrument { public: string Name (); void SetName (string To); virtual void Display (); virtual void Update (int Millisec) = 0; protected: string name; }; // Instrument } // InDash #endif Code Segment 3 loop Discover _ Plugins; Dash _ Board.Display; Dash _ Board.Update (Increment); delay Duration (Increment/1000); end loop;
IndustryWatch April 2006 73 The type Digital_Speedometer is thus a subclass of Instru- ment, with a representation that is hidden from clients. This is a typical abstract data type declaration using the normal infor- mation hiding techniques of the language. All the attributes and operations of the base class Instrument are inherited but note that the Display and Update operations are overridden to change their behaviors. An additional hidden floating-point component named “Value” is added to the inherited component. Running the Application Now that the infrastructure is in place, the main program can be built and can be extended with individual plug-ins while it executes. Initially no plug-ins will exist but the application can be launched. No instruments will be displayed but the main pro- gram will iterate nonetheless. Plug-ins can be built separately in another window while the main program is running and they will be discovered on successive iterations as they are built. The main program will discover new plug-ins and dispatch to the corresponding Display and Update the routines for the individual ob- jects within the plug-ins. Details for how the plug-ins are compiled and linked are ignored here but the source code provided includes the full mechanisms required. When all the plug-ins are present the display for one iteration looks like Code Segment 6. The instruments’ states are updated as time passes and the displayed values change accordingly. As the example has shown, object- oriented programming languages offer de- velopers a safe, robust method for extend- ing the functionality of high-availability applications without first stopping execu- tion. By making additional instances of new subclasses available, plug-ins allow dynamic dispatching to replace a lower- level, comparatively unsafe mechanism. Although this kind of run-time extension is not new, dynamic dispatching in terms of abstract base classes provides a much more robust mechanism. The reader may be surprised that Ada, known for applica- tions with more static characteristics, can take advantage of this capability as well, especially the ability to dynamically link extensions. AdaCore New York, NY. (212) 620-7300. [www.adacore.com]. Code Segment 4 procedure Display is C : Cursor := First (Registry); begin while C /= No _ Element loop Element (C).Display; -- dynamically dispatches Next (C); end loop; Ada.Text _ IO.New _ Line; end Display; Code Segment 5 with InDash; package Speedometer is subtype Speed is Float range 0.0 .. 200.0; -- mph type Digital _ Speedometer is new InDash.Instrument with private; procedure Display (This : access Digital _ Speedometer); procedure Update (This : access Digital _ Speedometer; Millisec : Integer); ... private type Digital _ Speedometer is new InDash.Instrument with record Value : Speed; end record; end Speedometer; Code Segment 6 New York : 12:15:15 Stopwatch : <<0015>> Paris : 06:15:15:000 Fuel : 59.75 % Water : <**************** > Oil : <******** > Speed : 47 Miles per Hour
Advertiser Index 74 April 2006 RTC (Issn#1092-1524) magazine is published monthly at 905 Calle Amanecer, Ste. 250, San Clemente, CA 92673. Periodical postage paid at San Clemente and at additional mailing offices. POSTMASTER: Send address changes to RTC, 905 Calle Amanecer, Ste. 250, San Clemente, CA 92673. Acromag...............................................31 ........................... www.acromag.com ADLINK Technology, Inc. .......................11 .............. www.adlinktechnology.com. ARCOM ................................................23 ............................... www.arcom.com BitMicro Networks, Inc. ...........................6 ............................ www.bitmicro.com Catalyst Enterprises, Inc. ......................35 ........................www.getcatalyst.com CompactPCI Showcase .........................49 ........................................................ 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